DWC_pcie_unroll_wire_cpcie_usp_4x8.csr/project/jenkins/workspace/Esperanto_DV/soc_hal/esperanto-soc/dv/common/scripts/semifore_css/etsoc_esr.cssPE0_DWC_pcie_ctlcomponentPE0_DWC_pcie_ctlPE0_DWC_pcie_ctlDWC_pcie_unroll_wire_cpcie_usp_4x8.csr64327NAPE0_DWC_pcie_ctladdressmapPE0_DWC_pcie_ctl.AXI_SlaveaddressmapPE0_DWC_pcie_ctl.DBI_SlaveaddressmapPE0_DWC_pcie_ctl.AXI_SlaveAXI_SlaveDWC_pcie_unroll_wire_cpcie_usp_4x8.csr64325R/WPE0_DWC_pcie_ctl_AXI_SlaveDWC PCIE-EP Memory MapgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAPgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP0x00x81123AXI_SlavePE0_DWC_pcie_ctl.AXI_Slave0x00x1FF23AXI_Slave.PF0_ATU_CAPPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP0x00x0AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_00x40x4AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_00x80x8AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_00xC0xCAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_00x100x10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_00x140x14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_00x180x18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_00x1C0x1F0x200x20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_00x240xFF0x1000x100AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_00x1040x104AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_00x1080x108AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_00x10C0x10CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_00x1100x110AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_00x1140x114AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_00x1180x118AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_00x11C0x11F0x1200x120AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_00x1240x1FF0x2000x200AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_10x2040x204AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_10x2080x208AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10x20C0x20CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10x2100x210AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_10x2140x214AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10x2180x218AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10x21C0x21F0x2200x220AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10x2240x2FF0x3000x300AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_10x3040x304AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_10x3080x308AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_10x30C0x30CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_10x3100x310AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_10x3140x314AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_10x3180x318AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10x31C0x31F0x3200x320AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10x3240x3FF0x4000x400AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_20x4040x404AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_20x4080x408AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_20x40C0x40CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_20x4100x410AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_20x4140x414AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_20x4180x418AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_20x41C0x41F0x4200x420AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_20x4240x4FF0x5000x500AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_20x5040x504AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_20x5080x508AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_20x50C0x50CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_20x5100x510AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_20x5140x514AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_20x5180x518AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20x51C0x51F0x5200x520AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20x5240x5FF0x6000x600AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_30x6040x604AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_30x6080x608AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_30x60C0x60CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_30x6100x610AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_30x6140x614AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_30x6180x618AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_30x61C0x61F0x6200x620AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_30x6240x6FF0x7000x700AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_30x7040x704AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_30x7080x708AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_30x70C0x70CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_30x7100x710AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_30x7140x714AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_30x7180x718AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30x71C0x71F0x7200x720AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30x7240x7FF0x8000x800AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_40x8040x804AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_40x8080x808AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_40x80C0x80CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_40x8100x810AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_40x8140x814AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_40x8180x818AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_40x81C0x81F0x8200x820AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_40x8240x8FF0x9000x900AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_40x9040x904AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_40x9080x908AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_40x90C0x90CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_40x9100x910AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_40x9140x914AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_40x9180x918AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_40x91C0x91F0x9200x920AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_40x9240x9FF0xA000xA00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_50xA040xA04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_50xA080xA08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_50xA0C0xA0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_50xA100xA10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_50xA140xA14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_50xA180xA18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_50xA1C0xA1F0xA200xA20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_50xA240xAFF0xB000xB00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_50xB040xB04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_50xB080xB08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_50xB0C0xB0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_50xB100xB10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_50xB140xB14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_50xB180xB18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_50xB1C0xB1F0xB200xB20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_50xB240xBFF0xC000xC00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_60xC040xC04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_60xC080xC08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_60xC0C0xC0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_60xC100xC10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_60xC140xC14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_60xC180xC18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_60xC1C0xC1F0xC200xC20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_60xC240xCFF0xD000xD00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_60xD040xD04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_60xD080xD08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_60xD0C0xD0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_60xD100xD10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_60xD140xD14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_60xD180xD18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_60xD1C0xD1F0xD200xD20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_60xD240xDFF0xE000xE00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_70xE040xE04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_70xE080xE08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_70xE0C0xE0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_70xE100xE10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_70xE140xE14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_70xE180xE18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_70xE1C0xE1F0xE200xE20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_70xE240xEFF0xF000xF00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_70xF040xF04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_70xF080xF08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_70xF0C0xF0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_70xF100xF10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_70xF140xF14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_70xF180xF18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_70xF1C0xF1F0xF200xF20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_70xF240xFFF0x10000x1000AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_80x10040x1004AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_80x10080x1008AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_80x100C0x100CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_80x10100x1010AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_80x10140x1014AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_80x10180x1018AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_80x101C0x101F0x10200x1020AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_80x10240x10FF0x11000x1100AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_80x11040x1104AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_80x11080x1108AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_80x110C0x110CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_80x11100x1110AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_80x11140x1114AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_80x11180x1118AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_80x111C0x111F0x11200x1120AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_80x11240x11FF0x12000x1200AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_90x12040x1204AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_90x12080x1208AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_90x120C0x120CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_90x12100x1210AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_90x12140x1214AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_90x12180x1218AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_90x121C0x121F0x12200x1220AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_90x12240x12FF0x13000x1300AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_90x13040x1304AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_90x13080x1308AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_90x130C0x130CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_90x13100x1310AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_90x13140x1314AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_90x13180x1318AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_90x131C0x131F0x13200x1320AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_90x13240x13FF0x14000x1400AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_100x14040x1404AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_100x14080x1408AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_100x140C0x140CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_100x14100x1410AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_100x14140x1414AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_100x14180x1418AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_100x141C0x141F0x14200x1420AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_100x14240x14FF0x15000x1500AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_100x15040x1504AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_100x15080x1508AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_100x150C0x150CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_100x15100x1510AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_100x15140x1514AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_100x15180x1518AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_100x151C0x151F0x15200x1520AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_100x15240x15FF0x16000x1600AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_110x16040x1604AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_110x16080x1608AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_110x160C0x160CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_110x16100x1610AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_110x16140x1614AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_110x16180x1618AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_110x161C0x161F0x16200x1620AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_110x16240x16FF0x17000x1700AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_110x17040x1704AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_110x17080x1708AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_110x170C0x170CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_110x17100x1710AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_110x17140x1714AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_110x17180x1718AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_110x171C0x171F0x17200x1720AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_110x17240x17FF0x18000x1800AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_120x18040x1804AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_120x18080x1808AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_120x180C0x180CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_120x18100x1810AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_120x18140x1814AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_120x18180x1818AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_120x181C0x181F0x18200x1820AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_120x18240x18FF0x19000x1900AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_120x19040x1904AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_120x19080x1908AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_120x190C0x190CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_120x19100x1910AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_120x19140x1914AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_120x19180x1918AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_120x191C0x191F0x19200x1920AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_120x19240x19FF0x1A000x1A00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_130x1A040x1A04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_130x1A080x1A08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_130x1A0C0x1A0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_130x1A100x1A10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_130x1A140x1A14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_130x1A180x1A18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_130x1A1C0x1A1F0x1A200x1A20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_130x1A240x1AFF0x1B000x1B00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_130x1B040x1B04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_130x1B080x1B08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_130x1B0C0x1B0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_130x1B100x1B10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_130x1B140x1B14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_130x1B180x1B18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_130x1B1C0x1B1F0x1B200x1B20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_130x1B240x1BFF0x1C000x1C00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_140x1C040x1C04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_140x1C080x1C08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_140x1C0C0x1C0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_140x1C100x1C10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_140x1C140x1C14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_140x1C180x1C18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_140x1C1C0x1C1F0x1C200x1C20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_140x1C240x1CFF0x1D000x1D00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_140x1D040x1D04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_140x1D080x1D08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_140x1D0C0x1D0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_140x1D100x1D10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_140x1D140x1D14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_140x1D180x1D18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_140x1D1C0x1D1F0x1D200x1D20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_140x1D240x1DFF0x1E000x1E00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_150x1E040x1E04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_150x1E080x1E08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_150x1E0C0x1E0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_150x1E100x1E10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_150x1E140x1E14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_150x1E180x1E18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_150x1E1C0x1E1F0x1E200x1E20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_150x1E240x1EFF0x1F000x1F00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_150x1F040x1F04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_150x1F080x1F08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_150x1F0C0x1F0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_150x1F100x1F10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_150x1F140x1F14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_150x1F180x1F18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_150x1F1C0x1F1F0x1F200x1F20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_150x1F240x20FF0x21000x2100AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_16PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_160x21040x2104AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_16PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_160x21080x2108AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_16PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_160x210C0x210CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_16PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_160x21100x2110AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_16PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_160x21140x2114AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_16PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_160x21180x2118AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_160x211C0x211F0x21200x2120AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_160x21240x22FF0x23000x2300AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_17PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_170x23040x2304AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_17PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_170x23080x2308AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_17PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_170x230C0x230CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_17PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_170x23100x2310AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_17PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_170x23140x2314AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_17PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_170x23180x2318AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_170x231C0x231F0x23200x2320AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_170x23240x24FF0x25000x2500AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_18PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_180x25040x2504AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_18PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_180x25080x2508AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_18PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_180x250C0x250CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_18PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_180x25100x2510AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_18PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_180x25140x2514AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_18PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_180x25180x2518AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_180x251C0x251F0x25200x2520AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_180x25240x26FF0x27000x2700AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_19PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_190x27040x2704AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_19PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_190x27080x2708AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_19PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_190x270C0x270CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_19PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_190x27100x2710AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_19PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_190x27140x2714AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_19PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_190x27180x2718AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_190x271C0x271F0x27200x2720AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_190x27240x28FF0x29000x2900AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_20PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_200x29040x2904AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_20PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_200x29080x2908AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_20PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_200x290C0x290CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_20PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_200x29100x2910AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_20PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_200x29140x2914AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_20PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_200x29180x2918AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_200x291C0x291F0x29200x2920AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_200x29240x2AFF0x2B000x2B00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_21PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_210x2B040x2B04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_21PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_210x2B080x2B08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_21PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_210x2B0C0x2B0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_21PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_210x2B100x2B10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_21PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_210x2B140x2B14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_21PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_210x2B180x2B18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_210x2B1C0x2B1F0x2B200x2B20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_210x2B240x2CFF0x2D000x2D00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_22PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_220x2D040x2D04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_22PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_220x2D080x2D08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_22PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_220x2D0C0x2D0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_22PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_220x2D100x2D10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_22PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_220x2D140x2D14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_22PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_220x2D180x2D18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_220x2D1C0x2D1F0x2D200x2D20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_220x2D240x2EFF0x2F000x2F00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_23PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_230x2F040x2F04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_23PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_230x2F080x2F08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_23PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_230x2F0C0x2F0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_23PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_230x2F100x2F10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_23PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_230x2F140x2F14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_23PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_230x2F180x2F18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_230x2F1C0x2F1F0x2F200x2F20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_230x2F240x30FF0x31000x3100AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_24PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_240x31040x3104AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_24PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_240x31080x3108AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_24PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_240x310C0x310CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_24PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_240x31100x3110AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_24PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_240x31140x3114AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_24PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_240x31180x3118AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_240x311C0x311F0x31200x3120AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_240x31240x32FF0x33000x3300AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_25PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_250x33040x3304AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_25PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_250x33080x3308AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_25PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_250x330C0x330CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_25PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_250x33100x3310AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_25PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_250x33140x3314AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_25PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_250x33180x3318AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_250x331C0x331F0x33200x3320AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_250x33240x34FF0x35000x3500AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_26PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_260x35040x3504AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_26PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_260x35080x3508AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_26PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_260x350C0x350CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_26PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_260x35100x3510AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_26PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_260x35140x3514AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_26PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_260x35180x3518AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_260x351C0x351F0x35200x3520AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_260x35240x36FF0x37000x3700AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_27PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_270x37040x3704AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_27PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_270x37080x3708AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_27PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_270x370C0x370CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_27PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_270x37100x3710AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_27PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_270x37140x3714AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_27PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_270x37180x3718AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_270x371C0x371F0x37200x3720AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_270x37240x38FF0x39000x3900AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_28PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_280x39040x3904AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_28PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_280x39080x3908AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_28PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_280x390C0x390CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_28PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_280x39100x3910AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_28PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_280x39140x3914AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_28PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_280x39180x3918AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_280x391C0x391F0x39200x3920AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_280x39240x3AFF0x3B000x3B00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_29PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_290x3B040x3B04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_29PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_290x3B080x3B08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_29PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_290x3B0C0x3B0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_29PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_290x3B100x3B10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_29PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_290x3B140x3B14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_29PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_290x3B180x3B18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_290x3B1C0x3B1F0x3B200x3B20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_290x3B240x3CFF0x3D000x3D00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_30PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_300x3D040x3D04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_30PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_300x3D080x3D08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_30PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_300x3D0C0x3D0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_30PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_300x3D100x3D10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_30PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_300x3D140x3D14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_30PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_300x3D180x3D18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_300x3D1C0x3D1F0x3D200x3D20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_300x3D240x3EFF0x3F000x3F00AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_31PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_310x3F040x3F04AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_31PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_310x3F080x3F08AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_31PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_310x3F0C0x3F0CAXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_31PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_310x3F100x3F10AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_31PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_310x3F140x3F14AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_31PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_310x3F180x3F18AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_310x3F1C0x3F1F0x3F200x3F20AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31PE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_310x3F240x1FF230x1FF240x7FFFF0x800000x81123AXI_Slave.PF0_DMA_CAPPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP0x800000x80000AXI_Slave.PF0_DMA_CAP.DMA_CTRL_DATA_ARB_PRIOR_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CTRL_DATA_ARB_PRIOR_OFF0x800040x800070x800080x80008AXI_Slave.PF0_DMA_CAP.DMA_CTRL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CTRL_OFF0x8000C0x8000CAXI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_EN_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_EN_OFF0x800100x80010AXI_Slave.PF0_DMA_CAP.DMA_WRITE_DOORBELL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_DOORBELL_OFF0x800140x800170x800180x80018AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF0x8001C0x8001CAXI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF0x800200x8002B0x8002C0x8002CAXI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_EN_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_EN_OFF0x800300x80030AXI_Slave.PF0_DMA_CAP.DMA_READ_DOORBELL_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_DOORBELL_OFF0x800340x800370x800380x80038AXI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF0x8003C0x8003CAXI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF0x800400x8004B0x8004C0x8004CAXI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_STATUS_OFF0x800500x800530x800540x80054AXI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_MASK_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_MASK_OFF0x800580x80058AXI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_CLEAR_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_CLEAR_OFF0x8005C0x8005CAXI_Slave.PF0_DMA_CAP.DMA_WRITE_ERR_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ERR_STATUS_OFF0x800600x80060AXI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_LOW_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_LOW_OFF0x800640x80064AXI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_HIGH_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_HIGH_OFF0x800680x80068AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_LOW_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_LOW_OFF0x8006C0x8006CAXI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_HIGH_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_HIGH_OFF0x800700x80070AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH01_IMWR_DATA_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH01_IMWR_DATA_OFF0x800740x80074AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH23_IMWR_DATA_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH23_IMWR_DATA_OFF0x800780x80078AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH45_IMWR_DATA_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH45_IMWR_DATA_OFF0x8007C0x8007CAXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH67_IMWR_DATA_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH67_IMWR_DATA_OFF0x800800x8008F0x800900x80090AXI_Slave.PF0_DMA_CAP.DMA_WRITE_LINKED_LIST_ERR_EN_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_LINKED_LIST_ERR_EN_OFF0x800940x8009F0x800A00x800A0AXI_Slave.PF0_DMA_CAP.DMA_READ_INT_STATUS_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_INT_STATUS_OFF0x800A40x800A70x800A80x800A8AXI_Slave.PF0_DMA_CAP.DMA_READ_INT_MASK_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_INT_MASK_OFF0x800AC0x800ACAXI_Slave.PF0_DMA_CAP.DMA_READ_INT_CLEAR_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_INT_CLEAR_OFF0x800B00x800B30x800B40x800B4AXI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_LOW_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_LOW_OFF0x800B80x800B8AXI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_HIGH_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_HIGH_OFF0x800BC0x800C30x800C40x800C4AXI_Slave.PF0_DMA_CAP.DMA_READ_LINKED_LIST_ERR_EN_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_LINKED_LIST_ERR_EN_OFF0x800C80x800CB0x800CC0x800CCAXI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_LOW_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_LOW_OFF0x800D00x800D0AXI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_HIGH_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_HIGH_OFF0x800D40x800D4AXI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_LOW_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_LOW_OFF0x800D80x800D8AXI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_HIGH_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_HIGH_OFF0x800DC0x800DCAXI_Slave.PF0_DMA_CAP.DMA_READ_CH01_IMWR_DATA_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CH01_IMWR_DATA_OFF0x800E00x800E0AXI_Slave.PF0_DMA_CAP.DMA_READ_CH23_IMWR_DATA_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CH23_IMWR_DATA_OFF0x800E40x800E4AXI_Slave.PF0_DMA_CAP.DMA_READ_CH45_IMWR_DATA_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CH45_IMWR_DATA_OFF0x800E80x800E8AXI_Slave.PF0_DMA_CAP.DMA_READ_CH67_IMWR_DATA_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CH67_IMWR_DATA_OFF0x800EC0x801070x801080x80108AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF0x8010C0x8010CAXI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF0x801100x801170x801180x80118AXI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF0x8011C0x8011CAXI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFFPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF0x801200x801FF0x802000x80200AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_00x802040x80204AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_00x802080x80208AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_00x8020C0x8020CAXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_00x802100x80210AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_00x802140x80214AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_00x802180x80218AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_00x8021C0x8021CAXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_00x802200x80220AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_00x802240x802FF0x803000x80300AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_00x803040x80304AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_00x803080x80308AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_00x8030C0x8030CAXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_00x803100x80310AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_00x803140x80314AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_00x803180x80318AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_00x8031C0x8031CAXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_00x803200x80320AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_0PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_00x803240x803FF0x804000x80400AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_10x804040x80404AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_10x804080x80408AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_10x8040C0x8040CAXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_10x804100x80410AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_10x804140x80414AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_10x804180x80418AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_10x8041C0x8041CAXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_10x804200x80420AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_10x804240x804FF0x805000x80500AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_10x805040x80504AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_10x805080x80508AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_10x8050C0x8050CAXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_10x805100x80510AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_10x805140x80514AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_10x805180x80518AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_10x8051C0x8051CAXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_10x805200x80520AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_1PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_10x805240x805FF0x806000x80600AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_20x806040x80604AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_20x806080x80608AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_20x8060C0x8060CAXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_20x806100x80610AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_20x806140x80614AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_20x806180x80618AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_20x8061C0x8061CAXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_20x806200x80620AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_20x806240x806FF0x807000x80700AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_20x807040x80704AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_20x807080x80708AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_20x8070C0x8070CAXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_20x807100x80710AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_20x807140x80714AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_20x807180x80718AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_20x8071C0x8071CAXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_20x807200x80720AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_2PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_20x807240x807FF0x808000x80800AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_30x808040x80804AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_30x808080x80808AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_30x8080C0x8080CAXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_30x808100x80810AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_30x808140x80814AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_30x808180x80818AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_30x8081C0x8081CAXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_30x808200x80820AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_30x808240x808FF0x809000x80900AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_30x809040x80904AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_30x809080x80908AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_30x8090C0x8090CAXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_30x809100x80910AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_30x809140x80914AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_30x809180x80918AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_30x8091C0x8091CAXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_30x809200x80920AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_3PE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_30x809240x81123groupPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAPPF0_ATU_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr258190x0R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAPATU Por Logic StructureregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_0IATU_REGION_CTRL_1_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1290x0R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr71When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr83When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr95Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr108When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr128Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_0IATU_REGION_CTRL_2_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3370x4R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr150MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr162TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr182TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr194TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr207Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr219Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr242TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr259Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr280Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr294DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr314CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr326Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr336Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3740x8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr362Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr373Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3900xCR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr389Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_0IATU_LIMIT_ADDR_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4170x10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr406Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr416Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4460x14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr445When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4600x18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr459Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4920x20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr479Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr491Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_0IATU_REGION_CTRL_1_OFF_INBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6050x100R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr506When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr519When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr532When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr545When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr558When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr570Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr584When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr604Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_0IATU_REGION_CTRL_2_OFF_INBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9000x104R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr630MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr655BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr673Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr684TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr695TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr707ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr720TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr734Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr753Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr766PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr782Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr798Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr817Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr832CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr844Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr889Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr899Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_0IATU_LWR_BASE_ADDR_OFF_INBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9370x108R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr925Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr936Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_0IATU_UPPER_BASE_ADDR_OFF_INBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9510x10CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr950Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_0IATU_LIMIT_ADDR_OFF_INBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9780x110R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr967Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr977Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_0IATU_LWR_TARGET_ADDR_OFF_INBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10170x114R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1003Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1016Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10330x118R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1032Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10650x120R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1052Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1064Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_1IATU_REGION_CTRL_1_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11680x200R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1079When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1090When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1099This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1110When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1122When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1134Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1147When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1167Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_1IATU_REGION_CTRL_2_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13760x204R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1189MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1201TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1221TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1233TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1246Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1258Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1281TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1298Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1319Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1333DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1353CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1365Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1375Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14130x208R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1401Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1412Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14290x20CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1428Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_1IATU_LIMIT_ADDR_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14560x210R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1445Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1455Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14850x214R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1484When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14990x218R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1498Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15310x220R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1518Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1530Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_1IATU_REGION_CTRL_1_OFF_INBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16440x300R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1545When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1558When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1571When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1584When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1597When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1609Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1623When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1643Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_1IATU_REGION_CTRL_2_OFF_INBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19390x304R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1669MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1694BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1712Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1723TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1734TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1746ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1759TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1773Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1792Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1805PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1821Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1837Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1856Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1871CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1883Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1928Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1938Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_1IATU_LWR_BASE_ADDR_OFF_INBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19760x308R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1964Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1975Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_1IATU_UPPER_BASE_ADDR_OFF_INBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19900x30CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr1989Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_1IATU_LIMIT_ADDR_OFF_INBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20170x310R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2006Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2016Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_1IATU_LWR_TARGET_ADDR_OFF_INBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20560x314R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2042Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2055Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20720x318R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2071Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21040x320R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2091Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2103Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_2IATU_REGION_CTRL_1_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22070x400R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2118When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2129When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2138This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2149When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2161When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2173Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2186When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2206Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_2IATU_REGION_CTRL_2_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24150x404R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2228MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2240TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2260TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2272TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2285Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2297Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2320TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2337Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2358Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2372DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2392CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2404Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2414Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24520x408R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2440Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2451Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24680x40CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2467Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_2IATU_LIMIT_ADDR_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24950x410R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2484Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2494Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25240x414R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2523When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25380x418R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2537Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25700x420R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2557Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2569Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_2IATU_REGION_CTRL_1_OFF_INBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26830x500R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2584When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2597When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2610When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2623When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2636When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2648Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2662When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2682Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_2IATU_REGION_CTRL_2_OFF_INBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29780x504R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2708MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2733BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2751Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2762TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2773TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2785ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2798TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2812Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2831Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2844PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2860Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2876Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2895Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2910CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2922Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2967Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr2977Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_2IATU_LWR_BASE_ADDR_OFF_INBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30150x508R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3003Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3014Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_2IATU_UPPER_BASE_ADDR_OFF_INBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30290x50CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3028Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_2IATU_LIMIT_ADDR_OFF_INBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30560x510R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3045Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3055Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_2IATU_LWR_TARGET_ADDR_OFF_INBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30950x514R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3081Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3094Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31110x518R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3110Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31430x520R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3130Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3142Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_3IATU_REGION_CTRL_1_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32460x600R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3157When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3168When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3177This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3188When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3200When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3212Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3225When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3245Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_3IATU_REGION_CTRL_2_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34540x604R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3267MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3279TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3299TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3311TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3324Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3336Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3359TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3376Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3397Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3411DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3431CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3443Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3453Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34910x608R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3479Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3490Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35070x60CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3506Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_3IATU_LIMIT_ADDR_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35340x610R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3523Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3533Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35630x614R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3562When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35770x618R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3576Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36090x620R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3596Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3608Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_3IATU_REGION_CTRL_1_OFF_INBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37220x700R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3623When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3636When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3649When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3662When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3675When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3687Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3701When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3721Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_3IATU_REGION_CTRL_2_OFF_INBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40170x704R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3747MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3772BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3790Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3801TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3812TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3824ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3837TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3851Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3870Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3883PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3899Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3915Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3934Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3949CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr3961Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4006Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4016Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_3IATU_LWR_BASE_ADDR_OFF_INBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40540x708R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4042Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4053Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_3IATU_UPPER_BASE_ADDR_OFF_INBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40680x70CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4067Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_3IATU_LIMIT_ADDR_OFF_INBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40950x710R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4084Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4094Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_3IATU_LWR_TARGET_ADDR_OFF_INBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41340x714R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4120Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4133Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41500x718R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4149Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41820x720R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4169Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4181Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_4IATU_REGION_CTRL_1_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42850x800R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4196When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4207When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4216This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4227When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4239When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4251Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4264When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4284Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_4IATU_REGION_CTRL_2_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44930x804R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4306MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4318TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4338TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4350TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4363Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4375Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4398TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4415Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4436Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4450DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4470CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4482Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4492Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45300x808R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4518Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4529Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45460x80CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4545Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_4IATU_LIMIT_ADDR_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45730x810R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4562Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4572Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46020x814R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4601When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46160x818R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4615Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46480x820R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4635Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4647Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_4IATU_REGION_CTRL_1_OFF_INBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47610x900R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4662When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4675When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4688When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4701When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4714When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4726Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4740When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4760Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_4IATU_REGION_CTRL_2_OFF_INBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50560x904R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4786MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4811BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4829Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4840TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4851TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4863ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4876TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4890Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4909Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4922PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4938Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4954Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4973Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr4988CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5000Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5045Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5055Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_4IATU_LWR_BASE_ADDR_OFF_INBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50930x908R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5081Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5092Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_4IATU_UPPER_BASE_ADDR_OFF_INBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51070x90CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5106Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_4IATU_LIMIT_ADDR_OFF_INBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51340x910R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5123Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5133Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_4IATU_LWR_TARGET_ADDR_OFF_INBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51730x914R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5159Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5172Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51890x918R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5188Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52210x920R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5208Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5220Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_5IATU_REGION_CTRL_1_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53240xA00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5235When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5246When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5255This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5266When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5278When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5290Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5303When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5323Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_5IATU_REGION_CTRL_2_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55320xA04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5345MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5357TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5377TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5389TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5402Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5414Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5437TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5454Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5475Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5489DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5509CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5521Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5531Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55690xA08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5557Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5568Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55850xA0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5584Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_5IATU_LIMIT_ADDR_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56120xA10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5601Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5611Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56410xA14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5640When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56550xA18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5654Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56870xA20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5674Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5686Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_5IATU_REGION_CTRL_1_OFF_INBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58000xB00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5701When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5714When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5727When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5740When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5753When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5765Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5779When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5799Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_5IATU_REGION_CTRL_2_OFF_INBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60950xB04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5825MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5850BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5868Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5879TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5890TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5902ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5915TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5929Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5948Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5961PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5977Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr5993Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6012Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6027CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6039Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6084Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6094Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_5IATU_LWR_BASE_ADDR_OFF_INBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61320xB08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6120Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6131Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_5IATU_UPPER_BASE_ADDR_OFF_INBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61460xB0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6145Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_5IATU_LIMIT_ADDR_OFF_INBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61730xB10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6162Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6172Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_5IATU_LWR_TARGET_ADDR_OFF_INBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62120xB14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6198Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6211Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62280xB18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6227Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62600xB20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6247Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6259Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_6IATU_REGION_CTRL_1_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63630xC00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6274When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6285When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6294This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6305When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6317When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6329Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6342When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6362Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_6IATU_REGION_CTRL_2_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr65710xC04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6384MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6396TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6416TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6428TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6441Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6453Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6476TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6493Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6514Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6528DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6548CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6560Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6570Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr66080xC08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6596Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6607Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr66240xC0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6623Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_6IATU_LIMIT_ADDR_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr66510xC10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6640Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6650Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr66800xC14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6679When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr66940xC18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6693Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr67260xC20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6713Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6725Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_6IATU_REGION_CTRL_1_OFF_INBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr68390xD00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6740When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6753When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6766When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6779When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6792When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6804Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6818When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6838Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_6IATU_REGION_CTRL_2_OFF_INBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr71340xD04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6864MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6889BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6907Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6918TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6929TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6941ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6954TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6968Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr6987Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7000PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7016Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7032Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7051Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7066CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7078Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7123Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7133Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_6IATU_LWR_BASE_ADDR_OFF_INBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr71710xD08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7159Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7170Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_6IATU_UPPER_BASE_ADDR_OFF_INBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr71850xD0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7184Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_6IATU_LIMIT_ADDR_OFF_INBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr72120xD10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7201Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7211Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_6IATU_LWR_TARGET_ADDR_OFF_INBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr72510xD14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7237Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7250Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr72670xD18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7266Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr72990xD20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7286Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7298Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_7IATU_REGION_CTRL_1_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr74020xE00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7313When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7324When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7333This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7344When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7356When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7368Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7381When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7401Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_7IATU_REGION_CTRL_2_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr76100xE04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7423MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7435TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7455TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7467TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7480Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7492Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7515TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7532Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7553Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7567DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7587CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7599Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7609Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr76470xE08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7635Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7646Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr76630xE0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7662Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_7IATU_LIMIT_ADDR_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr76900xE10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7679Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7689Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr77190xE14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7718When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr77330xE18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7732Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr77650xE20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7752Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7764Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_7IATU_REGION_CTRL_1_OFF_INBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr78780xF00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7779When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7792When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7805When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7818When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7831When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7843Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7857When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7877Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_7IATU_REGION_CTRL_2_OFF_INBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr81730xF04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7903MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7928BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7946Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7957TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7968TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7980ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr7993TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8007Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8026Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8039PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8055Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8071Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8090Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8105CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8117Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8162Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8172Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_7IATU_LWR_BASE_ADDR_OFF_INBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr82100xF08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8198Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8209Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_7IATU_UPPER_BASE_ADDR_OFF_INBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr82240xF0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8223Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_7IATU_LIMIT_ADDR_OFF_INBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr82510xF10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8240Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8250Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_7IATU_LWR_TARGET_ADDR_OFF_INBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr82900xF14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8276Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8289Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr83060xF18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8305Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr83380xF20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8325Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8337Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_8IATU_REGION_CTRL_1_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr84410x1000R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8352When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8363When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8372This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8383When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8395When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8407Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8420When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8440Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_8IATU_REGION_CTRL_2_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr86490x1004R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8462MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8474TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8494TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8506TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8519Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8531Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8554TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8571Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8592Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8606DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8626CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8638Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8648Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr86860x1008R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8674Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8685Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr87020x100CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8701Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_8IATU_LIMIT_ADDR_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr87290x1010R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8718Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8728Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr87580x1014R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8757When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr87720x1018R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8771Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr88040x1020R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8791Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8803Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_8IATU_REGION_CTRL_1_OFF_INBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr89170x1100R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8818When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8831When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8844When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8857When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8870When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8882Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8896When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8916Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_8IATU_REGION_CTRL_2_OFF_INBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr92120x1104R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8942MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8967BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8985Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr8996TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9007TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9019ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9032TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9046Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9065Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9078PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9094Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9110Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9129Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9144CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9156Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9201Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9211Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_8IATU_LWR_BASE_ADDR_OFF_INBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr92490x1108R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9237Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9248Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_8IATU_UPPER_BASE_ADDR_OFF_INBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr92630x110CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9262Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_8IATU_LIMIT_ADDR_OFF_INBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr92900x1110R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9279Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9289Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_8IATU_LWR_TARGET_ADDR_OFF_INBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr93290x1114R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9315Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9328Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr93450x1118R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9344Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr93770x1120R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9364Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9376Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_9IATU_REGION_CTRL_1_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr94800x1200R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9391When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9402When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9411This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9422When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9434When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9446Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9459When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9479Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_9IATU_REGION_CTRL_2_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr96880x1204R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9501MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9513TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9533TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9545TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9558Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9570Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9593TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9610Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9631Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9645DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9665CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9677Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9687Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr97250x1208R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9713Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9724Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr97410x120CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9740Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_9IATU_LIMIT_ADDR_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr97680x1210R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9757Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9767Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr97970x1214R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9796When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr98110x1218R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9810Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr98430x1220R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9830Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9842Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_9IATU_REGION_CTRL_1_OFF_INBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr99560x1300R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9857When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9870When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9883When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9896When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9909When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9921Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9935When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9955Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_9IATU_REGION_CTRL_2_OFF_INBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr102510x1304R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr9981MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10006BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10024Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10035TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10046TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10058ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10071TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10085Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10104Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10117PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10133Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10149Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10168Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10183CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10195Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10240Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10250Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_9IATU_LWR_BASE_ADDR_OFF_INBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr102880x1308R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10276Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10287Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_9IATU_UPPER_BASE_ADDR_OFF_INBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr103020x130CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10301Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_9IATU_LIMIT_ADDR_OFF_INBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr103290x1310R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10318Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10328Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_9IATU_LWR_TARGET_ADDR_OFF_INBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr103680x1314R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10354Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10367Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr103840x1318R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10383Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr104160x1320R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10403Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10415Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_10IATU_REGION_CTRL_1_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr105190x1400R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10430When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10441When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10450This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10461When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10473When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10485Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10498When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10518Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_10IATU_REGION_CTRL_2_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr107270x1404R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10540MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10552TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10572TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10584TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10597Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10609Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10632TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10649Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10670Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10684DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10704CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10716Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10726Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr107640x1408R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10752Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10763Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr107800x140CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10779Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_10IATU_LIMIT_ADDR_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr108070x1410R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10796Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10806Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr108360x1414R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10835When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr108500x1418R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10849Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr108820x1420R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10869Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10881Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_10IATU_REGION_CTRL_1_OFF_INBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr109950x1500R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10896When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10909When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10922When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10935When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10948When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10960Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10974When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr10994Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_10IATU_REGION_CTRL_2_OFF_INBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr112900x1504R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11020MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11045BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11063Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11074TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11085TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11097ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11110TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11124Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11143Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11156PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11172Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11188Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11207Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11222CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11234Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11279Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11289Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_10IATU_LWR_BASE_ADDR_OFF_INBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr113270x1508R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11315Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11326Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_10IATU_UPPER_BASE_ADDR_OFF_INBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr113410x150CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11340Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_10IATU_LIMIT_ADDR_OFF_INBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr113680x1510R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11357Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11367Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_10IATU_LWR_TARGET_ADDR_OFF_INBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr114070x1514R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11393Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11406Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr114230x1518R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11422Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr114550x1520R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11442Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11454Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_11IATU_REGION_CTRL_1_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr115580x1600R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11469When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11480When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11489This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11500When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11512When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11524Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11537When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11557Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_11IATU_REGION_CTRL_2_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr117660x1604R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11579MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11591TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11611TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11623TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11636Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11648Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11671TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11688Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11709Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11723DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11743CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11755Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11765Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr118030x1608R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11791Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11802Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr118190x160CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11818Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_11IATU_LIMIT_ADDR_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr118460x1610R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11835Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11845Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr118750x1614R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11874When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr118890x1618R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11888Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr119210x1620R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11908Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11920Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_11IATU_REGION_CTRL_1_OFF_INBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr120340x1700R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11935When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11948When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11961When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11974When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11987When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr11999Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12013When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12033Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_11IATU_REGION_CTRL_2_OFF_INBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr123290x1704R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12059MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12084BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12102Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12113TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12124TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12136ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12149TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12163Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12182Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12195PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12211Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12227Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12246Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12261CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12273Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12318Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12328Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_11IATU_LWR_BASE_ADDR_OFF_INBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr123660x1708R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12354Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12365Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_11IATU_UPPER_BASE_ADDR_OFF_INBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr123800x170CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12379Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_11IATU_LIMIT_ADDR_OFF_INBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr124070x1710R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12396Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12406Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_11IATU_LWR_TARGET_ADDR_OFF_INBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr124460x1714R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12432Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12445Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr124620x1718R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12461Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr124940x1720R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12481Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12493Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_12IATU_REGION_CTRL_1_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr125970x1800R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12508When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12519When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12528This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12539When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12551When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12563Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12576When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12596Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_12IATU_REGION_CTRL_2_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr128050x1804R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12618MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12630TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12650TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12662TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12675Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12687Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12710TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12727Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12748Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12762DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12782CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12794Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12804Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr128420x1808R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12830Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12841Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr128580x180CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12857Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_12IATU_LIMIT_ADDR_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr128850x1810R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12874Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12884Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr129140x1814R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12913When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr129280x1818R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12927Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr129600x1820R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12947Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12959Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_12IATU_REGION_CTRL_1_OFF_INBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr130730x1900R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12974When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr12987When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13000When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13013When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13026When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13038Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13052When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13072Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_12IATU_REGION_CTRL_2_OFF_INBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr133680x1904R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13098MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13123BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13141Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13152TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13163TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13175ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13188TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13202Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13221Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13234PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13250Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13266Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13285Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13300CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13312Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13357Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13367Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_12IATU_LWR_BASE_ADDR_OFF_INBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr134050x1908R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13393Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13404Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_12IATU_UPPER_BASE_ADDR_OFF_INBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr134190x190CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13418Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_12IATU_LIMIT_ADDR_OFF_INBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr134460x1910R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13435Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13445Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_12IATU_LWR_TARGET_ADDR_OFF_INBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr134850x1914R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13471Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13484Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr135010x1918R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13500Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr135330x1920R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13520Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13532Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_13IATU_REGION_CTRL_1_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr136360x1A00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13547When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13558When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13567This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13578When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13590When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13602Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13615When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13635Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_13IATU_REGION_CTRL_2_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr138440x1A04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13657MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13669TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13689TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13701TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13714Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13726Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13749TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13766Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13787Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13801DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13821CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13833Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13843Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr138810x1A08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13869Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13880Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr138970x1A0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13896Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_13IATU_LIMIT_ADDR_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr139240x1A10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13913Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13923Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr139530x1A14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13952When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr139670x1A18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13966Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr139990x1A20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13986Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr13998Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_13IATU_REGION_CTRL_1_OFF_INBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr141120x1B00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14013When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14026When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14039When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14052When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14065When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14077Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14091When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14111Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_13IATU_REGION_CTRL_2_OFF_INBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr144070x1B04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14137MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14162BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14180Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14191TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14202TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14214ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14227TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14241Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14260Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14273PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14289Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14305Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14324Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14339CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14351Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14396Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14406Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_13IATU_LWR_BASE_ADDR_OFF_INBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr144440x1B08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14432Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14443Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_13IATU_UPPER_BASE_ADDR_OFF_INBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr144580x1B0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14457Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_13IATU_LIMIT_ADDR_OFF_INBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr144850x1B10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14474Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14484Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_13IATU_LWR_TARGET_ADDR_OFF_INBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr145240x1B14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14510Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14523Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr145400x1B18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14539Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr145720x1B20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14559Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14571Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_14IATU_REGION_CTRL_1_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr146750x1C00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14586When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14597When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14606This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14617When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14629When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14641Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14654When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14674Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_14IATU_REGION_CTRL_2_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr148830x1C04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14696MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14708TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14728TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14740TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14753Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14765Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14788TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14805Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14826Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14840DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14860CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14872Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14882Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr149200x1C08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14908Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14919Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr149360x1C0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14935Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_14IATU_LIMIT_ADDR_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr149630x1C10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14952Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14962Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr149920x1C14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr14991When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr150060x1C18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15005Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr150380x1C20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15025Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15037Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_14IATU_REGION_CTRL_1_OFF_INBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr151510x1D00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15052When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15065When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15078When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15091When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15104When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15116Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15130When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15150Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_14IATU_REGION_CTRL_2_OFF_INBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr154460x1D04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15176MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15201BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15219Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15230TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15241TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15253ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15266TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15280Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15299Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15312PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15328Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15344Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15363Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15378CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15390Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15435Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15445Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_14IATU_LWR_BASE_ADDR_OFF_INBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr154830x1D08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15471Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15482Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_14IATU_UPPER_BASE_ADDR_OFF_INBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr154970x1D0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15496Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_14IATU_LIMIT_ADDR_OFF_INBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr155240x1D10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15513Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15523Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_14IATU_LWR_TARGET_ADDR_OFF_INBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr155630x1D14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15549Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15562Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr155790x1D18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15578Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr156110x1D20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15598Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15610Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_15IATU_REGION_CTRL_1_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr157140x1E00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15625When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15636When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15645This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15656When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15668When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15680Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15693When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15713Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_15IATU_REGION_CTRL_2_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr159220x1E04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15735MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15747TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15767TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15779TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15792Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15804Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15827TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15844Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15865Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15879DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15899CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15911Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15921Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr159590x1E08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15947Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15958Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr159750x1E0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15974Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_15IATU_LIMIT_ADDR_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr160020x1E10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr15991Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16001Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr160310x1E14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16030When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr160450x1E18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16044Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr160770x1E20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16064Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16076Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_15IATU_REGION_CTRL_1_OFF_INBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr161900x1F00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16091When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16104When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16117When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16130When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16143When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16155Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16169When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16189Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_15IATU_REGION_CTRL_2_OFF_INBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr164850x1F04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16215MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16240BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16258Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16269TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16280TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16292ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16305TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16319Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16338Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16351PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16367Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16383Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16402Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16417CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16429Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16474Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16484Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_15IATU_LWR_BASE_ADDR_OFF_INBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr165220x1F08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16510Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16521Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_15IATU_UPPER_BASE_ADDR_OFF_INBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr165360x1F0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16535Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_15IATU_LIMIT_ADDR_OFF_INBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr165630x1F10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16552Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16562Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_15IATU_LWR_TARGET_ADDR_OFF_INBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr166020x1F14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16588Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16601Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr166180x1F18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16617Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr166500x1F20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16637Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16649Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_16IATU_REGION_CTRL_1_OFF_INBOUND_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr167630x2100R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16664When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16677When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16690When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16703When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16716When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16728Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16742When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16762Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_16IATU_REGION_CTRL_2_OFF_INBOUND_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr170580x2104R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16788MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16813BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16831Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16842TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16853TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16865ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16878TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16892Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16911Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16924PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16940Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16956Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16975Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr16990CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17002Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17047Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17057Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_16IATU_LWR_BASE_ADDR_OFF_INBOUND_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr170950x2108R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17083Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17094Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_16IATU_UPPER_BASE_ADDR_OFF_INBOUND_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr171090x210CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17108Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_16IATU_LIMIT_ADDR_OFF_INBOUND_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr171360x2110R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17125Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17135Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_16IATU_LWR_TARGET_ADDR_OFF_INBOUND_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr171750x2114R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17161Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17174Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr171910x2118R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17190Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr172230x2120R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17210Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17222Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_17IATU_REGION_CTRL_1_OFF_INBOUND_17PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr173360x2300R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17237When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17250When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17263When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17276When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17289When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17301Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17315When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17335Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_17IATU_REGION_CTRL_2_OFF_INBOUND_17PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr176310x2304R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17361MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17386BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17404Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17415TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17426TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17438ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17451TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17465Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17484Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17497PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17513Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17529Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17548Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17563CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17575Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17620Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17630Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_17IATU_LWR_BASE_ADDR_OFF_INBOUND_17PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr176680x2308R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17656Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17667Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_17IATU_UPPER_BASE_ADDR_OFF_INBOUND_17PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr176820x230CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17681Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_17IATU_LIMIT_ADDR_OFF_INBOUND_17PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr177090x2310R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17698Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17708Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_17IATU_LWR_TARGET_ADDR_OFF_INBOUND_17PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr177480x2314R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17734Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17747Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr177640x2318R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17763Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr177960x2320R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17783Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17795Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_18IATU_REGION_CTRL_1_OFF_INBOUND_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr179090x2500R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17810When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17823When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17836When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17849When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17862When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17874Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17888When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17908Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_18IATU_REGION_CTRL_2_OFF_INBOUND_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr182040x2504R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17934MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17959BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17977Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17988TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr17999TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18011ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18024TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18038Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18057Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18070PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18086Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18102Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18121Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18136CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18148Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18193Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18203Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_18IATU_LWR_BASE_ADDR_OFF_INBOUND_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr182410x2508R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18229Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18240Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_18IATU_UPPER_BASE_ADDR_OFF_INBOUND_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr182550x250CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18254Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_18IATU_LIMIT_ADDR_OFF_INBOUND_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr182820x2510R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18271Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18281Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_18IATU_LWR_TARGET_ADDR_OFF_INBOUND_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr183210x2514R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18307Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18320Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr183370x2518R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18336Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr183690x2520R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18356Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18368Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_19IATU_REGION_CTRL_1_OFF_INBOUND_19PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr184820x2700R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18383When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18396When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18409When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18422When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18435When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18447Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18461When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18481Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_19IATU_REGION_CTRL_2_OFF_INBOUND_19PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr187770x2704R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18507MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18532BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18550Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18561TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18572TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18584ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18597TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18611Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18630Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18643PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18659Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18675Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18694Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18709CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18721Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18766Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18776Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_19IATU_LWR_BASE_ADDR_OFF_INBOUND_19PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr188140x2708R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18802Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18813Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_19IATU_UPPER_BASE_ADDR_OFF_INBOUND_19PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr188280x270CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18827Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_19IATU_LIMIT_ADDR_OFF_INBOUND_19PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr188550x2710R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18844Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18854Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_19IATU_LWR_TARGET_ADDR_OFF_INBOUND_19PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr188940x2714R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18880Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18893Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr189100x2718R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18909Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr189420x2720R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18929Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18941Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_20IATU_REGION_CTRL_1_OFF_INBOUND_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr190550x2900R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18956When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18969When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18982When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr18995When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19008When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19020Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19034When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19054Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_20IATU_REGION_CTRL_2_OFF_INBOUND_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr193500x2904R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19080MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19105BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19123Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19134TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19145TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19157ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19170TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19184Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19203Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19216PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19232Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19248Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19267Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19282CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19294Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19339Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19349Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_20IATU_LWR_BASE_ADDR_OFF_INBOUND_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr193870x2908R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19375Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19386Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_20IATU_UPPER_BASE_ADDR_OFF_INBOUND_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr194010x290CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19400Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_20IATU_LIMIT_ADDR_OFF_INBOUND_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr194280x2910R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19417Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19427Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_20IATU_LWR_TARGET_ADDR_OFF_INBOUND_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr194670x2914R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19453Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19466Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr194830x2918R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19482Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr195150x2920R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19502Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19514Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_21IATU_REGION_CTRL_1_OFF_INBOUND_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr196280x2B00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19529When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19542When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19555When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19568When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19581When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19593Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19607When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19627Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_21IATU_REGION_CTRL_2_OFF_INBOUND_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr199230x2B04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19653MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19678BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19696Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19707TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19718TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19730ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19743TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19757Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19776Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19789PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19805Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19821Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19840Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19855CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19867Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19912Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19922Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_21IATU_LWR_BASE_ADDR_OFF_INBOUND_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr199600x2B08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19948Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19959Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_21IATU_UPPER_BASE_ADDR_OFF_INBOUND_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr199740x2B0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19973Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_21IATU_LIMIT_ADDR_OFF_INBOUND_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr200010x2B10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr19990Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20000Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_21IATU_LWR_TARGET_ADDR_OFF_INBOUND_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr200400x2B14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20026Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20039Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr200560x2B18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20055Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr200880x2B20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20075Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20087Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_22IATU_REGION_CTRL_1_OFF_INBOUND_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr202010x2D00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20102When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20115When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20128When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20141When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20154When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20166Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20180When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20200Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_22IATU_REGION_CTRL_2_OFF_INBOUND_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr204960x2D04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20226MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20251BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20269Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20280TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20291TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20303ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20316TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20330Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20349Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20362PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20378Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20394Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20413Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20428CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20440Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20485Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20495Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_22IATU_LWR_BASE_ADDR_OFF_INBOUND_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr205330x2D08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20521Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20532Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_22IATU_UPPER_BASE_ADDR_OFF_INBOUND_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr205470x2D0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20546Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_22IATU_LIMIT_ADDR_OFF_INBOUND_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr205740x2D10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20563Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20573Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_22IATU_LWR_TARGET_ADDR_OFF_INBOUND_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr206130x2D14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20599Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20612Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr206290x2D18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20628Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr206610x2D20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20648Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20660Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_23IATU_REGION_CTRL_1_OFF_INBOUND_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr207740x2F00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20675When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20688When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20701When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20714When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20727When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20739Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20753When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20773Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_23IATU_REGION_CTRL_2_OFF_INBOUND_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr210690x2F04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20799MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20824BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20842Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20853TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20864TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20876ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20889TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20903Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20922Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20935PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20951Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20967Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr20986Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21001CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21013Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21058Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21068Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_23IATU_LWR_BASE_ADDR_OFF_INBOUND_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr211060x2F08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21094Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21105Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_23IATU_UPPER_BASE_ADDR_OFF_INBOUND_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr211200x2F0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21119Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_23IATU_LIMIT_ADDR_OFF_INBOUND_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr211470x2F10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21136Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21146Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_23IATU_LWR_TARGET_ADDR_OFF_INBOUND_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr211860x2F14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21172Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21185Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr212020x2F18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21201Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr212340x2F20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21221Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21233Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_24IATU_REGION_CTRL_1_OFF_INBOUND_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr213470x3100R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21248When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21261When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21274When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21287When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21300When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21312Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21326When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21346Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_24IATU_REGION_CTRL_2_OFF_INBOUND_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr216420x3104R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21372MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21397BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21415Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21426TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21437TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21449ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21462TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21476Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21495Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21508PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21524Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21540Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21559Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21574CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21586Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21631Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21641Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_24IATU_LWR_BASE_ADDR_OFF_INBOUND_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr216790x3108R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21667Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21678Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_24IATU_UPPER_BASE_ADDR_OFF_INBOUND_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr216930x310CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21692Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_24IATU_LIMIT_ADDR_OFF_INBOUND_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr217200x3110R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21709Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21719Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_24IATU_LWR_TARGET_ADDR_OFF_INBOUND_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr217590x3114R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21745Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21758Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr217750x3118R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21774Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr218070x3120R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21794Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21806Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_25IATU_REGION_CTRL_1_OFF_INBOUND_25PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr219200x3300R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21821When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21834When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21847When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21860When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21873When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21885Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21899When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21919Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_25IATU_REGION_CTRL_2_OFF_INBOUND_25PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr222150x3304R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21945MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21970BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21988Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr21999TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22010TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22022ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22035TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22049Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22068Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22081PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22097Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22113Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22132Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22147CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22159Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22204Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22214Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_25IATU_LWR_BASE_ADDR_OFF_INBOUND_25PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr222520x3308R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22240Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22251Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_25IATU_UPPER_BASE_ADDR_OFF_INBOUND_25PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr222660x330CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22265Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_25IATU_LIMIT_ADDR_OFF_INBOUND_25PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr222930x3310R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22282Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22292Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_25IATU_LWR_TARGET_ADDR_OFF_INBOUND_25PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr223320x3314R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22318Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22331Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr223480x3318R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22347Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr223800x3320R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22367Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22379Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_26IATU_REGION_CTRL_1_OFF_INBOUND_26PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr224930x3500R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22394When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22407When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22420When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22433When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22446When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22458Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22472When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22492Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_26IATU_REGION_CTRL_2_OFF_INBOUND_26PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr227880x3504R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22518MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22543BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22561Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22572TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22583TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22595ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22608TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22622Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22641Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22654PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22670Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22686Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22705Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22720CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22732Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22777Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22787Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_26IATU_LWR_BASE_ADDR_OFF_INBOUND_26PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr228250x3508R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22813Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22824Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_26IATU_UPPER_BASE_ADDR_OFF_INBOUND_26PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr228390x350CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22838Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_26IATU_LIMIT_ADDR_OFF_INBOUND_26PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr228660x3510R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22855Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22865Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_26IATU_LWR_TARGET_ADDR_OFF_INBOUND_26PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr229050x3514R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22891Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22904Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr229210x3518R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22920Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr229530x3520R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22940Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22952Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_27IATU_REGION_CTRL_1_OFF_INBOUND_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr230660x3700R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22967When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22980When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr22993When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23006When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23019When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23031Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23045When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23065Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_27IATU_REGION_CTRL_2_OFF_INBOUND_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr233610x3704R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23091MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23116BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23134Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23145TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23156TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23168ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23181TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23195Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23214Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23227PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23243Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23259Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23278Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23293CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23305Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23350Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23360Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_27IATU_LWR_BASE_ADDR_OFF_INBOUND_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr233980x3708R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23386Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23397Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_27IATU_UPPER_BASE_ADDR_OFF_INBOUND_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr234120x370CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23411Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_27IATU_LIMIT_ADDR_OFF_INBOUND_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr234390x3710R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23428Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23438Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_27IATU_LWR_TARGET_ADDR_OFF_INBOUND_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr234780x3714R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23464Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23477Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr234940x3718R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23493Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr235260x3720R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23513Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23525Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_28IATU_REGION_CTRL_1_OFF_INBOUND_28PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr236390x3900R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23540When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23553When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23566When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23579When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23592When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23604Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23618When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23638Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_28IATU_REGION_CTRL_2_OFF_INBOUND_28PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr239340x3904R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23664MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23689BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23707Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23718TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23729TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23741ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23754TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23768Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23787Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23800PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23816Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23832Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23851Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23866CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23878Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23923Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23933Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_28IATU_LWR_BASE_ADDR_OFF_INBOUND_28PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr239710x3908R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23959Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23970Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_28IATU_UPPER_BASE_ADDR_OFF_INBOUND_28PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr239850x390CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr23984Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_28IATU_LIMIT_ADDR_OFF_INBOUND_28PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr240120x3910R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24001Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24011Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_28IATU_LWR_TARGET_ADDR_OFF_INBOUND_28PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr240510x3914R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24037Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24050Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr240670x3918R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24066Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr240990x3920R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24086Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24098Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_29IATU_REGION_CTRL_1_OFF_INBOUND_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr242120x3B00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24113When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24126When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24139When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24152When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24165When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24177Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24191When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24211Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_29IATU_REGION_CTRL_2_OFF_INBOUND_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr245070x3B04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24237MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24262BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24280Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24291TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24302TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24314ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24327TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24341Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24360Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24373PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24389Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24405Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24424Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24439CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24451Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24496Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24506Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_29IATU_LWR_BASE_ADDR_OFF_INBOUND_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr245440x3B08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24532Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24543Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_29IATU_UPPER_BASE_ADDR_OFF_INBOUND_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr245580x3B0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24557Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_29IATU_LIMIT_ADDR_OFF_INBOUND_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr245850x3B10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24574Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24584Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_29IATU_LWR_TARGET_ADDR_OFF_INBOUND_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr246240x3B14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24610Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24623Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr246400x3B18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24639Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr246720x3B20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24659Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24671Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_30IATU_REGION_CTRL_1_OFF_INBOUND_30PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr247850x3D00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24686When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24699When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24712When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24725When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24738When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24750Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24764When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24784Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_30IATU_REGION_CTRL_2_OFF_INBOUND_30PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr250800x3D04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24810MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24835BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24853Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24864TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24875TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24887ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24900TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24914Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24933Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24946PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24962Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24978Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr24997Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25012CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25024Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25069Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25079Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_30IATU_LWR_BASE_ADDR_OFF_INBOUND_30PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr251170x3D08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25105Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25116Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_30IATU_UPPER_BASE_ADDR_OFF_INBOUND_30PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr251310x3D0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25130Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_30IATU_LIMIT_ADDR_OFF_INBOUND_30PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr251580x3D10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25147Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25157Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_30IATU_LWR_TARGET_ADDR_OFF_INBOUND_30PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr251970x3D14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25183Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25196Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr252130x3D18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25212Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr252450x3D20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25232Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25244Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_31IATU_REGION_CTRL_1_OFF_INBOUND_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr253580x3F00R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25259When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25272When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25285When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25298When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25311When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25323Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25337When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25357Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_31IATU_REGION_CTRL_2_OFF_INBOUND_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr256530x3F04R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25383MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25408BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25426Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25437TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25448TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25460ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25473TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25487Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25506Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25519PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25535Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25551Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25570Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25585CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25597Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25642Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25652Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_31IATU_LWR_BASE_ADDR_OFF_INBOUND_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr256900x3F08R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25678Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25689Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_31IATU_UPPER_BASE_ADDR_OFF_INBOUND_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr257040x3F0CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25703Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_31IATU_LIMIT_ADDR_OFF_INBOUND_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr257310x3F10R/W0x00000fffPE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25720Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25730Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_31IATU_LWR_TARGET_ADDR_OFF_INBOUND_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr257700x3F14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25756Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25769Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr257860x3F18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25785Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr258180x3F20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25805Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25817Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RgroupPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAPPF0_DMA_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr321670x80000R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAPDMA Port Logic StructureregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CTRL_DATA_ARB_PRIOR_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CTRL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_EN_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_DOORBELL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_EN_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_DOORBELL_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_MASK_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_CLEAR_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ERR_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_LOW_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_HIGH_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_LOW_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_HIGH_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH01_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH23_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH45_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH67_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_LINKED_LIST_ERR_EN_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_INT_STATUS_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_INT_MASK_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_INT_CLEAR_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_LOW_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_HIGH_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_LINKED_LIST_ERR_EN_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_LOW_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_HIGH_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_LOW_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_HIGH_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CH01_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CH23_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CH45_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CH67_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFFregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_0registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_1registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_2registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_3registerPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CTRL_DATA_ARB_PRIOR_OFFDMA_CTRL_DATA_ARB_PRIOR_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr258970x0R/W0x00000688PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFFDMA Arbitration Scheme for TRGT1 Interface. This register is used to control traffic priorities among various sources that are delivered to your application through TRGT1 where 0x0 represents the highest priority. - Non-DMA Rx Requests - DMA Write Channel MRd Requests (DMA data requests and LL element/descriptor access) - DMA Read Channel MRd Requests (LL element/descriptor access) - DMA Read Channel MWr RequestsConcurrent traffic from channels with same priority are sorted according to Round-Robin arbitration rules.The arbitration priority defaults to Non-DMA requests (highest), Write Channel MRd, Read Channel MRd, Read Channel MWr.For more details, see the For more details, see the Internal Architecture section in the DMA chapter of the Databook.falsefalsefalsefalseRTRGT1_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25853Non-DMA Rx Requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 200x0R/WWR_CTRL_TRGT_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25865DMA Write Channel MRd Requests. For DMA data requests and LL element/descriptor access.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 530x1R/WRD_CTRL_TRGT_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25877DMA Read Channel MRd Requests. For LL element/descriptor access.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 860x2R/WRDBUFF_TRGT_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25888DMA Read Channel MWr Requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1190x3R/WRSVDP_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25896Reserved for future use.31120x00000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CTRL_OFFDMA_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr259730x8R/W0x00040004PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CTRL_OFFDMA Number of Channels Register.falsefalsefalsefalseNUM_DMA_WR_CHANPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25910Number of Write Channels. You can read this register to determine the number of write channels the DMA controller has been configured to support.300x4RRSVDP_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25918Reserved for future use.1540x000RNUM_DMA_RD_CHANPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25928Number of Read Channels. You can read this register to determine the number of read channels the DMA controller has been configured to support.19160x4RRSVDP_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25936Reserved for future use.23200x0RDIS_C2W_CACHE_WRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25950Disable DMA Write Channels "completion to memory write" context cache pre-fetch function.Note: For internal debugging only.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24240x0R/WDIS_C2W_CACHE_RDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25964Disable DMA Read Channels "completion to memory write" context cache pre-fetch function.Note: For internal debugging only.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 25250x0R/WRSVDP_26PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr25972Reserved for future use.31260x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_EN_OFFDMA_WRITE_ENGINE_EN_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr261320xCR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFFDMA Write Engine Enable Register.falsefalsefalsefalseDMA_WRITE_ENGINEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26027DMA Write Engine Enable. - 1: Enable - 0: Disable (Soft Reset)For normal operation, you must initially set this bit to "1", before any other software setup actions. You do not need to toggle or rewrite to this bit during normal operation.You should set this bit to "0" when you want to "Soft Reset" the DMA controller write logic. There are three possible reasons for resetting the DMA controller write logic: - The "Abort Interrupt Status" bit is set (in the "DMA Write Interrupt Status Register" DMA_WRITE_INT_STATUS_OFF), and any of the bits is in the "DMA Write Error Status Register" (DMA_WRITE_ERR_STATUS_OFF) are set. Resetting the DMA controller write logic re-initializes the control logic, ensuring that the next DMA write transfer is executed successfully. - You have executed the procedure outlined in "Stop Bit" , after which, the "Abort Interrupt Status" bit is set and the Channel Status field (CS) of the DMA write "DMA Channel Control 1 Register " (DMA_CH_CONTROL1_OFF_WRCH_0) is set to "Stopped." Resetting the DMA controller write logic re-initializes the control logic ensuring that the next DMA write transfer is executed successfully. - During software development, when you incorrectly program the DMA write engine.To "Soft Reset" the DMA controller write logic, you must: - De-assert the DMA write engine enable bit. - Wait for the DMA to complete any in-progress TLP transfer, by waiting until a read on the DMA write engine enable bit returns a "0". - Assert the DMA write engine enable bit.This "Soft Reset" does not clear the DMA configuration registers. The DMA write transfer does not start until you write to the "DMA Write Doorbell Register" (DMA_WRITE_DOORBELL_OFF).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26035Reserved for future use.1510x0000RDMA_WRITE_ENGINE_EN_HSHAKE_CH0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26046Enable Handshake for DMA Write Engine Channel 0.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 16160x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26057Enable Handshake for DMA Write Engine Channel 1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 17170x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26068Enable Handshake for DMA Write Engine Channel 2.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 18180x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26079Enable Handshake for DMA Write Engine Channel 3.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 19190x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26090Enable Handshake for DMA Write Engine Channel 4.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 20200x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26101Enable Handshake for DMA Write Engine Channel 5.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 21210x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26112Enable Handshake for DMA Write Engine Channel 6.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 22220x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26123Enable Handshake for DMA Write Engine Channel 7.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23230x0R/WRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26131Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_DOORBELL_OFFDMA_WRITE_DOORBELL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr261850x10R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFFDMA Write Doorbell Register.falsefalsefalsefalseWR_DOORBELL_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26155Doorbell Number. You must write the channel number to this register to start the DMA write transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. You do not need to toggle or write any other value to this register to start a new transfer.The range of this field is 0x0 to 0x7, and 0x0 corresponds to channel 0. Also note that a write to this field triggers the controller to exit L1 substates.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 200x0R/WRSVDP_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26163Reserved for future use.3030x0000000RWR_STOPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26184Stop. Set in conjunction with the Doorbell Number field. The DMA write channel stops issuing requests, sets the channel status to "Stopped", and asserts the "Abort" interrupt if it is enabled. Before setting the Stop bit, you must read the channel Status field (CS) of the "DMA Channel Control 1 Register " (DMA_CH_CONTROL1_OFF_WRCH_0) to ensure that the write channel is "Running" (transferring data).For more information, see "Stopping the DMA Transfer (Software Stop)."Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFFDMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr262670x18R/W0x00008421PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFFDMA Write Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for write channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to the arbitration routine. When the channel weight count is reached or DMA channel request transfer size reaches zero, the WWR arbiter selects the next channel to be processed. Your software must initialize this register before ringing the doorbell. For more details, see "Multichannel Arbitration". Value range is (0-0x1F) corresponding to (1-32) transaction requests.falsefalsefalsefalseWRITE_CHANNEL0_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26213Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 400x01R/WWRITE_CHANNEL1_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26228Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 950x01R/WWRITE_CHANNEL2_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26243Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 14100x01R/WWRITE_CHANNEL3_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26258Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 19150x01R/WRSVDP_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26266Reserved for future use.31200x000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFFDMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr263490x1CR/W0x00008421PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFFDMA Write Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for write channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to the arbitration routine. When the channel weight count is reached or DMA channel request transfer size reaches zero, the WWR arbiter selects the next channel to be processed. Your software must initialize this register before ringing the doorbell. For more details, see "Multichannel Arbitration". Value range is (0-0x1F) corresponding to (1-32) transaction requests.falsefalsefalsefalseWRITE_CHANNEL4_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26295Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 400x01R/WWRITE_CHANNEL5_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26310Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 950x01R/WWRITE_CHANNEL6_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26325Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 14100x01R/WWRITE_CHANNEL7_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26340Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 19150x01R/WRSVDP_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26348Reserved for future use.31200x000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_EN_OFFDMA_READ_ENGINE_EN_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr265070x2CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFFDMA Read Engine Enable Register.falsefalsefalsefalseDMA_READ_ENGINEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26402DMA Read Engine Enable. - 1: Enable - 0: Disable (Soft Reset)For normal operation, you must initially set this bit to "1", before any other software setup actions. You do not need to toggle or rewrite to this bit during normal operation.You should set this field to "0" when you want to "Soft Reset" the DMA controller read logic. There are three possible reasons for resetting the DMA controller read logic: - The "Abort Interrupt Status" bit is set (in the "DMA Read Interrupt Status Register" (DMA_READ_INT_STATUS_OFF), and any of the bits in the "DMA Read Error Status Low Register" (DMA_READ_ERR_STATUS_LOW_OFF) is set. Resetting the DMA controller read logic re-initializes the control logic, ensuring that the next DMA read transfer is executed successfully. - You have executed the procedure outlined in "Stop Bit", after which, the "Abort Interrupt Status" bit is set and the channel Status field (CS) of the DMA read "DMA Channel Control 1 Register " (DMA_CH_CONTROL1_OFF_WRCH_0) is set to "Stopped". Resetting the DMA controller read logic re-initializes the control logic ensuring that the next DMA read transfer is executed successfully. - During software development, when you incorrectly program the DMA read engine.To "Soft Reset" the DMA controller read logic, you must: - De-assert the DMA read engine enable bit. - Wait for the DMA to complete any in-progress TLP transfer, by waiting until a read on the DMA read engine enable bit returns a "0". - Assert the DMA read engine enable bit.This "Soft Reset" does not clear the DMA configuration registers. The DMA read transfer does not start until you write to the "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26410Reserved for future use.1510x0000RDMA_READ_ENGINE_EN_HSHAKE_CH0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26421Enable Handshake for DMA Read Engine Channel 0.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 16160x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26432Enable Handshake for DMA Read Engine Channel 1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 17170x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26443Enable Handshake for DMA Read Engine Channel 2.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 18180x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26454Enable Handshake for DMA Read Engine Channel 3.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 19190x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26465Enable Handshake for DMA Read Engine Channel 4.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 20200x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26476Enable Handshake for DMA Read Engine Channel 5.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 21210x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26487Enable Handshake for DMA Read Engine Channel 6.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 22220x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26498Enable Handshake for DMA Read Engine Channel 7.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23230x0R/WRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26506Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_DOORBELL_OFFDMA_READ_DOORBELL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr265580x30R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_DOORBELL_OFFDMA Read Doorbell Register.falsefalsefalsefalseRD_DOORBELL_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26528Doorbell Number. You must write 0x0 to this register to start the DMA read transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change.The range of this field is 0x0 to 0x7, and 0x0 corresponds to channel 0. Also note that a write to this field triggers the controller to exit L1 substates.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 200x0R/WRSVDP_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26536Reserved for future use.3030x0000000RRD_STOPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26557Stop. Set in conjunction with the Doorbell Number field. The DMA read channel stops issuing requests, sets the channel status to "Stopped", and asserts the "Abort" interrupt if it is enabled. Before setting the Stop bit, you must read the channel Status field (CS) of the "DMA Channel Control 1 Register " (DMA_CH_CONTROL1_OFF_RDCH_0) to ensure that the read channel is "Running" (transferring data).For more information, see "Stopping the DMA Transfer (Software Stop)".Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFFDMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr266350x38R/W0x00008421PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFFDMA Read Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for read channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to the arbitration routine. When the channel weight count is reached or DMA channel request transfer size reaches zero, the WWR arbiter selects the next channel to be processed. Your software must initialize this register before ringing the doorbell. For more details, see "Multichannel Arbitration". Value range is (0-0x1F) corresponding to (1-32) transaction requests.falsefalsefalsefalseREAD_CHANNEL0_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26584Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 400x01R/WREAD_CHANNEL1_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26598Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 950x01R/WREAD_CHANNEL2_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26612Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 14100x01R/WREAD_CHANNEL3_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26626Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 19150x01R/WRSVDP_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26634Reserved for future use.31200x000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFFDMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr267120x3CR/W0x00008421PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFFDMA Read Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for read channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to the arbitration routine. When the channel weight count is reached or DMA channel request transfer size reaches zero, the WWR arbiter selects the next channel to be processed. Your software must initialize this register before ringing the doorbell. For more details, see "Multichannel Arbitration". Value range is (0-0x1F) corresponding to (1-32) transaction requests.falsefalsefalsefalseREAD_CHANNEL4_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26661Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 400x01R/WREAD_CHANNEL5_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26675Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 950x01R/WREAD_CHANNEL6_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26689Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 14100x01R/WREAD_CHANNEL7_WEIGHTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26703Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 19150x01R/WRSVDP_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26711Reserved for future use.31200x000RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_STATUS_OFFDMA_WRITE_INT_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr267860x4CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFFDMA Write Interrupt Status Register.falsefalsefalsefalseWR_DONE_INT_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26742Done Interrupt Status. The DMA write channel has successfully completed the DMA transfer. For more details, see "Interrupts and Error Handling". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA write interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the DMA write interrupt Clear register to clear this interrupt bit. Note: You can write to this register to emulate interrupt generation, during software or hardware testing. A write to the address triggers an interrupt, but the DMA does not set the Done or Abort bits in this register.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 700x00R/WRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26750Reserved for future use.1580x00RWR_ABORT_INT_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26777Abort Interrupt Status. The DMA write channel has detected an error, or you manually stopped the transfer as described in "Error Handling Assistance by Remote Software". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA write interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the DMA write interrupt Clear register to clear this interrupt bit. Note: You can write to this register to emulate interrupt generation, during software or hardware testing. A write to the address triggers an interrupt, but the DMA does not set the Done or Abort bits in this register.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23160x00R/WRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26785Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_MASK_OFFDMA_WRITE_INT_MASK_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr268340x54R/W0x000f000fPE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFFDMA Write Interrupt Mask Register.falsefalsefalsefalseWR_DONE_INT_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26803Done Interrupt Mask. Prevents the Done interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 300xfR/W--740x0rRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26811Reserved for future use.1580x00RWR_ABORT_INT_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26825Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 19160xfR/W--23200x0rRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26833Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_CLEAR_OFFDMA_WRITE_INT_CLEAR_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr268860x58R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFFDMA Write Interrupt Clear Register.falsefalsefalsefalseWR_DONE_INT_CLEARPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26853Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: Reading from this self-clearing register field always returns a "0".300x0W--740x0rRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26861Reserved for future use.1580x00RWR_ABORT_INT_CLEARPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26877Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: Reading from this self-clearing register field always returns a "0".19160x0W--23200x0rRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26885Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ERR_STATUS_OFFDMA_WRITE_ERR_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr269480x5CR0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFFDMA Write Error Status RegisterfalsefalsefalsefalseAPP_READ_ERR_DETECTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26911Application Read Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading data from it. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA write interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Write Interrupt Clear Register" (DMA_WRITE_INT_CLEAR_OFF) to clear this error bit.700x00RRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26918Reserved for future use.1580x00RLINKLIST_ELEMENT_FETCH_ERR_DETECTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26940Linked List Element Fetch Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading a linked list element from local memory. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA write interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Write Interrupt Clear Register" (DMA_WRITE_INT_CLEAR_OFF) to clear this error bit.23160x00RRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26947Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_LOW_OFFDMA_WRITE_DONE_IMWR_LOW_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr269650x60R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFFDMA Write Done IMWr Address Low Register.falsefalsefalsefalseDMA_WRITE_DONE_LOW_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26964The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be "00" as this address must be dword aligned.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_HIGH_OFFDMA_WRITE_DONE_IMWR_HIGH_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr269810x64R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFFDMA Write Done IMWr Interrupt Address High Register.falsefalsefalsefalseDMA_WRITE_DONE_HIGH_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26980The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_LOW_OFFDMA_WRITE_ABORT_IMWR_LOW_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr269990x68R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFFDMA Write Abort IMWr Address Low Register.falsefalsefalsefalseDMA_WRITE_ABORT_LOW_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr26998The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP it generates. Bits [1:0] must be "00" as this address must be dword aligned.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_HIGH_OFFDMA_WRITE_ABORT_IMWR_HIGH_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr270150x6CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFFDMA Write Abort IMWr Address High Register.falsefalsefalsefalseDMA_WRITE_ABORT_HIGH_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27014The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH01_IMWR_DATA_OFFDMA_WRITE_CH01_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr270430x70R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFFDMA Write Channel 1 and 0 IMWr Data Register.falsefalsefalsefalseWR_CHANNEL_0_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27030The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 0.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1500x0000R/WWR_CHANNEL_1_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27042The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH23_IMWR_DATA_OFFDMA_WRITE_CH23_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr270710x74R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFFDMA Write Channel 3 and 2 IMWr Data Register.falsefalsefalsefalseWR_CHANNEL_2_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27058The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 2.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1500x0000R/WWR_CHANNEL_3_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27070The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 3.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH45_IMWR_DATA_OFFDMA_WRITE_CH45_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr270990x78R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFFDMA Write Channel 5 and 4 IMWr Data Register.falsefalsefalsefalseWR_CHANNEL_4_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27086The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 4.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1500x0000R/WWR_CHANNEL_5_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27098The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 5.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_CH67_IMWR_DATA_OFFDMA_WRITE_CH67_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr271270x7CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFFDMA Write Channel 7 and 6 IMWr Data Register.falsefalsefalsefalseWR_CHANNEL_6_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27114The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 6.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1500x0000R/WWR_CHANNEL_7_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27126The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 7.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_LINKED_LIST_ERR_EN_OFFDMA_WRITE_LINKED_LIST_ERR_EN_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr271850x90R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFFDMA Write Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel "done" interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel "abort" interrupts (local and remote).falsefalsefalsefalseWR_CHANNEL_LLRAIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27151Write Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the write channel remote abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Used in linked list mode only.For more details, see "Interrupt Handling".Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 300x0R/W--740x0rRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27159Reserved for future use.1580x00RWR_CHANNEL_LLLAIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27176Write Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the write channel local abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Used in linked list mode only.For more details, see "Interrupt Handling".Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 19160x0R/W--23200x0rRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27184Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_INT_STATUS_OFFDMA_READ_INT_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr272620xA0R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFFDMA Read Interrupt Status Register.falsefalsefalsefalseRD_DONE_INT_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27214Done Interrupt Status. The DMA read channel has successfully completed the DMA read transfer.Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the DMA read interrupt Clear register to clear this interrupt bit. Note: You can write to this register to emulate interrupt generation, during software or hardware testing. A write to the address triggers an interrupt, but the DMA does not set the Done or Abort bits in this register.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 700x00R/WRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27222Reserved for future use.1580x00RRD_ABORT_INT_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27253Abort Interrupt Status. The DMA read channel has detected an error, or you manually stopped the transfer as described in "Stopping the DMA Transfer (Software Stop)". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.You can read the "DMA Read Error Status Low Register" (DMA_READ_ERR_STATUS_LOW_OFF) and "DMA Read Error Status High Register" (DMA_READ_ERR_STATUS_HIGH_OFF) to determine the source of the error. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the DMA read interrupt Clear register to clear this interrupt bit. Note: You can write to this register to emulate interrupt generation, during software or hardware testing. A write to the address triggers an interrupt, but the DMA does not set the Done or Abort bits in this register.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23160x00R/WRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27261Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_INT_MASK_OFFDMA_READ_INT_MASK_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr273100xA8R/W0x000f000fPE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_INT_MASK_OFFDMA Read Interrupt Mask Register.falsefalsefalsefalseRD_DONE_INT_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27279Done Interrupt Mask. Prevents the Done interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 300xfR/W--740x0rRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27287Reserved for future use.1580x00RRD_ABORT_INT_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27301Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 19160xfR/W--23200x0rRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27309Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_INT_CLEAR_OFFDMA_READ_INT_CLEAR_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr273620xACR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFFDMA Read Interrupt Clear Register.falsefalsefalsefalseRD_DONE_INT_CLEARPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27329Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: Reading from this self-clearing register field always returns a "0".700x00WRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27337Reserved for future use.1580x00RRD_ABORT_INT_CLEARPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27353Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: Reading from this self-clearing register field always returns a "0".23160x00WRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27361Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_LOW_OFFDMA_READ_ERR_STATUS_LOW_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr274300xB4R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFFDMA Read Error Status Low Register.falsefalsefalsefalseAPP_WR_ERR_DETECTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27392Application Write Error Detected. The DMA read channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while writing data to it. This error is fatal. You must restart the transfer from the beginning, as the channel context is corrupted, and the transfer is not rolled back. For more details, see "Linked List Mode". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this clears all bits in this register, and also the DMA Read Error Status High register (DMA_READ_ERR_STATUS_HIGH_OFF).700x00RRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27399Reserved for future use.1580x00RLINK_LIST_ELEMENT_FETCH_ERR_DETECTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27422Linked List Element Fetch Error Detected. - The DMA read channel has received an error response from the AXI bus while reading a linked list element from local memory. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this clears all bits in this register, and also the DMA Read Error Status High register (DMA_READ_ERR_STATUS_HIGH_OFF).23160x00RRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27429Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_HIGH_OFFDMA_READ_ERR_STATUS_HIGH_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr275310xB8R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFFDMA Read Error Status High Register.falsefalsefalsefalseUNSUPPORTED_REQPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27457Unsupported Request. The DMA read channel has received a PCIe unsupported request completion status from the remote device in response to the MRd request. For more details, see "Linked List Mode". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this also clears the other error bits for the same channel in this register and in the DMA Read Error Status Low register.700x00RCPL_ABORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27481Completer Abort. The DMA read channel has received a PCIe completer abort completion status from the remote device in response to the MRd request. For more details, see "Linked List Mode".Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this also clears the other error bits for the same channel in this register and in the DMA Read Error Status Low register.1580x00RCPL_TIMEOUTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27504Completion Time Out. The DMA read channel has timed-out while waiting for the remote device to respond to the MRd request, or a malformed CplD has been received. For more details, see "Linked List Mode". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling" . - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this also clears the other error bits for the same channel in this register and in the DMA Read Error Status Low register.23160x00RDATA_POISIONINGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27530Data Poisoning. The DMA read channel has detected data poisoning in the completion from the remote device (in response to the MRd request).The DMA read channel will drop the completion and then be halted. The CX_FLT_MASK_UR_POIS filter rule does not affect this behavior.Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this also clears the other error bits for the same channel in this register and in the DMA Read Error Status Low register.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_LINKED_LIST_ERR_EN_OFFDMA_READ_LINKED_LIST_ERR_EN_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr275880xC4R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFFDMA Read Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel "done" interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel "abort" interrupts (local and remote).falsefalsefalsefalseRD_CHANNEL_LLRAIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27554Read Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the read channel Remote Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Used in linked list mode only.For more details, see "Interrupt Handling".Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 300x0R/W--740x0rRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27562Reserved for future use.1580x00RRD_CHANNEL_LLLAIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27579Read Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the read channel Local Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Used in linked list mode only.For more details, see "Interrupt Handling".Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 19160x0R/W--23200x0rRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27587Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_LOW_OFFDMA_READ_DONE_IMWR_LOW_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr276050xCCR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFFDMA Read Done IMWr Address Low Register.falsefalsefalsefalseDMA_READ_DONE_LOW_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27604The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be "00" as this address must be dword aligned.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_HIGH_OFFDMA_READ_DONE_IMWR_HIGH_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr276210xD0R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFFDMA Read Done IMWr Address High Register.falsefalsefalsefalseDMA_READ_DONE_HIGH_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27620The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_LOW_OFFDMA_READ_ABORT_IMWR_LOW_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr276380xD4R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFFDMA Read Abort IMWr Address Low Register.falsefalsefalsefalseDMA_READ_ABORT_LOW_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27637The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP. Bits [1:0] must be "00" as this address must be dword aligned.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_HIGH_OFFDMA_READ_ABORT_IMWR_HIGH_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr276540xD8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFFDMA Read Abort IMWr Address High Register.falsefalsefalsefalseDMA_READ_ABORT_HIGH_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27653The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CH01_IMWR_DATA_OFFDMA_READ_CH01_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr276820xDCR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFFDMA Read Channel 1 and 0 IMWr Data Register.falsefalsefalsefalseRD_CHANNEL_0_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27669The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 0.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1500x0000R/WRD_CHANNEL_1_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27681The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CH23_IMWR_DATA_OFFDMA_READ_CH23_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr277100xE0R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFFDMA Read Channel 3 and 2 IMWr Data Register.falsefalsefalsefalseRD_CHANNEL_2_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27697The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 2.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1500x0000R/WRD_CHANNEL_3_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27709The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 3.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CH45_IMWR_DATA_OFFDMA_READ_CH45_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr277380xE4R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFFDMA Read Channel 5 and 4 IMWr Data Register.falsefalsefalsefalseRD_CHANNEL_4_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27725The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 4.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1500x0000R/WRD_CHANNEL_5_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27737The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 5.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_CH67_IMWR_DATA_OFFDMA_READ_CH67_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr277660xE8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFFDMA Read Channel 7 and 6 IMWr Data Register.falsefalsefalsefalseRD_CHANNEL_6_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27753The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 6.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1500x0000R/WRD_CHANNEL_7_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27765The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 7.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFFDMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr278390x108R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFFDMA Write Engine Handshake Counter Channel 0/1/2/3 Register.falsefalsefalsefalseDMA_WRITE_ENGINE_HSHAKE_CNT_CH0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27780DMA handshake counter for DMA Write Engine Channel 0. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.400x00RRSVDP_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27787Reserved for future use.750x0RDMA_WRITE_ENGINE_HSHAKE_CNT_CH1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27797DMA handshake counter for DMA Write Engine Channel 1. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.1280x00RRSVDP_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27804Reserved for future use.15130x0RDMA_WRITE_ENGINE_HSHAKE_CNT_CH2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27814DMA handshake counter for DMA Write Engine Channel 2. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.20160x00RRSVDP_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27821Reserved for future use.23210x0RDMA_WRITE_ENGINE_HSHAKE_CNT_CH3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27831DMA handshake counter for DMA Write Engine Channel 3. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.28240x00RRSVDP_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27838Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFFDMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr279120x10CR0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFFDMA Write Engine Handshake Counter Channel 4/5/6/7 Register.falsefalsefalsefalseDMA_WRITE_ENGINE_HSHAKE_CNT_CH4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27853DMA handshake counter for DMA Write Engine Channel 4. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.400x00RRSVDP_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27860Reserved for future use.750x0RDMA_WRITE_ENGINE_HSHAKE_CNT_CH5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27870DMA handshake counter for DMA Write Engine Channel 5. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.1280x00RRSVDP_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27877Reserved for future use.15130x0RDMA_WRITE_ENGINE_HSHAKE_CNT_CH6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27887DMA handshake counter for DMA Write Engine Channel 6. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.20160x00RRSVDP_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27894Reserved for future use.23210x0RDMA_WRITE_ENGINE_HSHAKE_CNT_CH7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27904DMA handshake counter for DMA Write Engine Channel 7. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.28240x00RRSVDP_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27911Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFFDMA_READ_ENGINE_HSHAKE_CNT_LOW_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr279850x118R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFFDMA Read Engine Handshake Counter Channel 0/1/2/3 Register.falsefalsefalsefalseDMA_READ_ENGINE_HSHAKE_CNT_CH0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27926DMA handshake counter for DMA Read Engine Channel 0. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.400x00RRSVDP_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27933Reserved for future use.750x0RDMA_READ_ENGINE_HSHAKE_CNT_CH1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27943DMA handshake counter for DMA Read Engine Channel 1. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.1280x00RRSVDP_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27950Reserved for future use.15130x0RDMA_READ_ENGINE_HSHAKE_CNT_CH2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27960DMA handshake counter for DMA Read Engine Channel 2. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.20160x00RRSVDP_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27967Reserved for future use.23210x0RDMA_READ_ENGINE_HSHAKE_CNT_CH3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27977DMA handshake counter for DMA Read Engine Channel 3. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.28240x00RRSVDP_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27984Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFFDMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr280580x11CR0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFFDMA Read Engine Handshake Counter Channel 4/5/6/7 Register.falsefalsefalsefalseDMA_READ_ENGINE_HSHAKE_CNT_CH4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr27999DMA handshake counter for DMA Read Engine Channel 4. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.400x00RRSVDP_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28006Reserved for future use.750x0RDMA_READ_ENGINE_HSHAKE_CNT_CH5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28016DMA handshake counter for DMA Read Engine Channel 5. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.1280x00RRSVDP_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28023Reserved for future use.15130x0RDMA_READ_ENGINE_HSHAKE_CNT_CH6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28033DMA handshake counter for DMA Read Engine Channel 6. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.20160x00RRSVDP_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28040Reserved for future use.23210x0RDMA_READ_ENGINE_HSHAKE_CNT_CH7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28050DMA handshake counter for DMA Read Engine Channel 7. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.28240x00RRSVDP_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28057Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_0DMA_CH_CONTROL1_OFF_WRCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr283650x200R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0DMA Write Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28078Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28097Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28114Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28135Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28156Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28177Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Write Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28189Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28207Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28220Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28232Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28248Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Write Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_WRCH_0).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28260Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28282Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28296Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28310Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28324Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28336Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28350Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28364Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_0DMA_CH_CONTROL2_OFF_WRCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr284210x204R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0DMA Write Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28381Steering Tag (ST). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28393Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28406Processing Hints (PH). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28420TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_0DMA_TRANSFER_SIZE_OFF_WRCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr284520x208R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0DMA Write Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28451DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_0DMA_SAR_LOW_OFF_WRCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr284730x20CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0DMA Write SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28472Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Write: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_0DMA_SAR_HIGH_OFF_WRCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr284910x210R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0DMA Write SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28490Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_0DMA_DAR_LOW_OFF_WRCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr285120x214R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0DMA Write DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28511Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Write: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_0DMA_DAR_HIGH_OFF_WRCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr285310x218R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0DMA Write DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28530Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_0DMA_LLP_LOW_OFF_WRCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr285530x21CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0DMA Write Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28552Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_0DMA_LLP_HIGH_OFF_WRCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr285720x220R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0DMA Write Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28571Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_0DMA_CH_CONTROL1_OFF_RDCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr288790x300R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0DMA Read Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28592Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28611Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28628Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28649Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28670Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28691Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Read Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28703Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28721Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28734Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28746Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28762Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Read Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_RDCH_0).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28774Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28796Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28810Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28824Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28838Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28850Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28864Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28878Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_0DMA_CH_CONTROL2_OFF_RDCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr289350x304R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0DMA Read Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28895Steering Tag (ST). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28907Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28920Processing Hints (PH). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28934TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_0DMA_TRANSFER_SIZE_OFF_RDCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr289660x308R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0DMA Read Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28965DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_0DMA_SAR_LOW_OFF_RDCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr289870x30CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0DMA Read SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr28986Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Read: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_0DMA_SAR_HIGH_OFF_RDCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr290050x310R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0DMA Read SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29004Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_0DMA_DAR_LOW_OFF_RDCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr290260x314R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0DMA Read DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29025Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Read: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_0DMA_DAR_HIGH_OFF_RDCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr290440x318R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0DMA Read DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29043Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_0DMA_LLP_LOW_OFF_RDCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr290660x31CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0DMA Read Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29065Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_0DMA_LLP_HIGH_OFF_RDCH_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr290850x320R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0DMA Read Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29084Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_1DMA_CH_CONTROL1_OFF_WRCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr293920x400R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1DMA Write Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29105Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29124Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29141Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29162Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29183Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29204Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Write Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29216Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29234Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29247Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29259Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29275Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Write Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_WRCH_0).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29287Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29309Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29323Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29337Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29351Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29363Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29377Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29391Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_1DMA_CH_CONTROL2_OFF_WRCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr294480x404R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1DMA Write Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29408Steering Tag (ST). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29420Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29433Processing Hints (PH). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29447TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_1DMA_TRANSFER_SIZE_OFF_WRCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr294790x408R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1DMA Write Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29478DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_1DMA_SAR_LOW_OFF_WRCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr295000x40CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1DMA Write SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29499Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Write: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_1DMA_SAR_HIGH_OFF_WRCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr295180x410R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1DMA Write SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29517Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_1DMA_DAR_LOW_OFF_WRCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr295390x414R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1DMA Write DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29538Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Write: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_1DMA_DAR_HIGH_OFF_WRCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr295580x418R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1DMA Write DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29557Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_1DMA_LLP_LOW_OFF_WRCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr295800x41CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1DMA Write Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29579Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_1DMA_LLP_HIGH_OFF_WRCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr295990x420R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1DMA Write Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29598Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_1DMA_CH_CONTROL1_OFF_RDCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr299060x500R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1DMA Read Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29619Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29638Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29655Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29676Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29697Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29718Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Read Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29730Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29748Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29761Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29773Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29789Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Read Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_RDCH_0).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29801Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29823Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29837Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29851Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29865Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29877Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29891Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29905Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_1DMA_CH_CONTROL2_OFF_RDCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr299620x504R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1DMA Read Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29922Steering Tag (ST). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29934Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29947Processing Hints (PH). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29961TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_1DMA_TRANSFER_SIZE_OFF_RDCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr299930x508R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1DMA Read Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr29992DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_1DMA_SAR_LOW_OFF_RDCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr300140x50CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1DMA Read SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30013Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Read: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_1DMA_SAR_HIGH_OFF_RDCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr300320x510R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1DMA Read SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30031Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_1DMA_DAR_LOW_OFF_RDCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr300530x514R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1DMA Read DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30052Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Read: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_1DMA_DAR_HIGH_OFF_RDCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr300710x518R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1DMA Read DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30070Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_1DMA_LLP_LOW_OFF_RDCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr300930x51CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1DMA Read Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30092Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_1DMA_LLP_HIGH_OFF_RDCH_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr301120x520R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1DMA Read Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30111Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_2DMA_CH_CONTROL1_OFF_WRCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr304190x600R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2DMA Write Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30132Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30151Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30168Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30189Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30210Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30231Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Write Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30243Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30261Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30274Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30286Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30302Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Write Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_WRCH_0).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30314Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30336Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30350Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30364Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30378Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30390Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30404Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30418Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_2DMA_CH_CONTROL2_OFF_WRCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr304750x604R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2DMA Write Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30435Steering Tag (ST). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30447Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30460Processing Hints (PH). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30474TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_2DMA_TRANSFER_SIZE_OFF_WRCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr305060x608R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2DMA Write Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30505DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_2DMA_SAR_LOW_OFF_WRCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr305270x60CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2DMA Write SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30526Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Write: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_2DMA_SAR_HIGH_OFF_WRCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr305450x610R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2DMA Write SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30544Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_2DMA_DAR_LOW_OFF_WRCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr305660x614R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2DMA Write DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30565Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Write: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_2DMA_DAR_HIGH_OFF_WRCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr305850x618R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2DMA Write DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30584Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_2DMA_LLP_LOW_OFF_WRCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr306070x61CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2DMA Write Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30606Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_2DMA_LLP_HIGH_OFF_WRCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr306260x620R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2DMA Write Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30625Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_2DMA_CH_CONTROL1_OFF_RDCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr309330x700R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2DMA Read Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30646Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30665Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30682Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30703Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30724Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30745Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Read Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30757Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30775Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30788Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30800Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30816Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Read Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_RDCH_0).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30828Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30850Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30864Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30878Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30892Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30904Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30918Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30932Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_2DMA_CH_CONTROL2_OFF_RDCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr309890x704R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2DMA Read Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30949Steering Tag (ST). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30961Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30974Processing Hints (PH). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr30988TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_2DMA_TRANSFER_SIZE_OFF_RDCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr310200x708R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2DMA Read Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31019DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_2DMA_SAR_LOW_OFF_RDCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr310410x70CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2DMA Read SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31040Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Read: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_2DMA_SAR_HIGH_OFF_RDCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr310590x710R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2DMA Read SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31058Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_2DMA_DAR_LOW_OFF_RDCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr310800x714R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2DMA Read DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31079Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Read: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_2DMA_DAR_HIGH_OFF_RDCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr310980x718R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2DMA Read DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31097Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_2DMA_LLP_LOW_OFF_RDCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr311200x71CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2DMA Read Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31119Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_2DMA_LLP_HIGH_OFF_RDCH_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr311390x720R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2DMA Read Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31138Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_3DMA_CH_CONTROL1_OFF_WRCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr314460x800R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3DMA Write Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31159Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31178Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31195Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31216Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31237Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31258Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Write Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31270Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31288Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31301Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31313Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31329Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Write Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_WRCH_0).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31341Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31363Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31377Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31391Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31405Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31417Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31431Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31445Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_3DMA_CH_CONTROL2_OFF_WRCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr315020x804R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3DMA Write Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31462Steering Tag (ST). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31474Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31487Processing Hints (PH). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31501TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_3DMA_TRANSFER_SIZE_OFF_WRCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr315330x808R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3DMA Write Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31532DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_3DMA_SAR_LOW_OFF_WRCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr315540x80CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3DMA Write SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31553Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Write: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_3DMA_SAR_HIGH_OFF_WRCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr315720x810R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3DMA Write SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31571Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_3DMA_DAR_LOW_OFF_WRCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr315930x814R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3DMA Write DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31592Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Write: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_3DMA_DAR_HIGH_OFF_WRCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr316120x818R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3DMA Write DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31611Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_3DMA_LLP_LOW_OFF_WRCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr316340x81CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3DMA Write Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31633Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_3DMA_LLP_HIGH_OFF_WRCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr316530x820R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3DMA Write Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31652Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_3DMA_CH_CONTROL1_OFF_RDCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr319600x900R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3DMA Read Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31673Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31692Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31709Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31730Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31751Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31772Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Read Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31784Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31802Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31815Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31827Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31843Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Read Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_RDCH_0).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31855Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31877Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31891Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31905Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31919Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31931Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31945Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31959Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_3DMA_CH_CONTROL2_OFF_RDCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr320160x904R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3DMA Read Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31976Steering Tag (ST). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr31988Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32001Processing Hints (PH). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32015TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_3DMA_TRANSFER_SIZE_OFF_RDCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr320470x908R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3DMA Read Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32046DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_3DMA_SAR_LOW_OFF_RDCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr320680x90CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3DMA Read SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32067Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Read: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_3DMA_SAR_HIGH_OFF_RDCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr320860x910R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3DMA Read SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32085Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_3DMA_DAR_LOW_OFF_RDCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr321070x914R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3DMA Read DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32106Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Read: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_3DMA_DAR_HIGH_OFF_RDCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr321250x918R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3DMA Read DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32124Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_3DMA_LLP_LOW_OFF_RDCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr321470x91CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3DMA Read Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32146Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.AXI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_3DMA_LLP_HIGH_OFF_RDCH_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr321660x920R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3DMA Read Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32165Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WaddressmapPE0_DWC_pcie_ctl.DBI_SlaveDBI_SlaveDWC_pcie_unroll_wire_cpcie_usp_4x8.csr64326R/WPE0_DWC_pcie_ctl_DBI_SlaveDWC PCIE-EP Memory MapgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAPgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP0x00x81123DBI_SlavePE0_DWC_pcie_ctl.DBI_Slave0x00x1FF23DBI_Slave.PF0_ATU_CAPPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP0x00x0DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_00x40x4DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_00x80x8DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_00xC0xCDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_00x100x10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_00x140x14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_00x180x18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_00x1C0x1F0x200x20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_00x240xFF0x1000x100DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_00x1040x104DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_00x1080x108DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_00x10C0x10CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_00x1100x110DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_00x1140x114DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_00x1180x118DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_00x11C0x11F0x1200x120DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_00x1240x1FF0x2000x200DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_10x2040x204DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_10x2080x208DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10x20C0x20CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10x2100x210DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_10x2140x214DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10x2180x218DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10x21C0x21F0x2200x220DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10x2240x2FF0x3000x300DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_10x3040x304DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_10x3080x308DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_10x30C0x30CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_10x3100x310DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_10x3140x314DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_10x3180x318DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10x31C0x31F0x3200x320DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10x3240x3FF0x4000x400DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_20x4040x404DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_20x4080x408DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_20x40C0x40CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_20x4100x410DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_20x4140x414DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_20x4180x418DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_20x41C0x41F0x4200x420DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_20x4240x4FF0x5000x500DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_20x5040x504DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_20x5080x508DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_20x50C0x50CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_20x5100x510DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_20x5140x514DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_20x5180x518DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20x51C0x51F0x5200x520DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20x5240x5FF0x6000x600DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_30x6040x604DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_30x6080x608DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_30x60C0x60CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_30x6100x610DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_30x6140x614DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_30x6180x618DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_30x61C0x61F0x6200x620DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_30x6240x6FF0x7000x700DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_30x7040x704DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_30x7080x708DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_30x70C0x70CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_30x7100x710DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_30x7140x714DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_30x7180x718DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30x71C0x71F0x7200x720DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30x7240x7FF0x8000x800DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_40x8040x804DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_40x8080x808DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_40x80C0x80CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_40x8100x810DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_40x8140x814DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_40x8180x818DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_40x81C0x81F0x8200x820DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_40x8240x8FF0x9000x900DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_40x9040x904DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_40x9080x908DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_40x90C0x90CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_40x9100x910DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_40x9140x914DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_40x9180x918DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_40x91C0x91F0x9200x920DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_40x9240x9FF0xA000xA00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_50xA040xA04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_50xA080xA08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_50xA0C0xA0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_50xA100xA10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_50xA140xA14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_50xA180xA18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_50xA1C0xA1F0xA200xA20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_50xA240xAFF0xB000xB00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_50xB040xB04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_50xB080xB08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_50xB0C0xB0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_50xB100xB10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_50xB140xB14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_50xB180xB18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_50xB1C0xB1F0xB200xB20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_50xB240xBFF0xC000xC00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_60xC040xC04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_60xC080xC08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_60xC0C0xC0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_60xC100xC10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_60xC140xC14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_60xC180xC18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_60xC1C0xC1F0xC200xC20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_60xC240xCFF0xD000xD00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_60xD040xD04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_60xD080xD08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_60xD0C0xD0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_60xD100xD10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_60xD140xD14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_60xD180xD18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_60xD1C0xD1F0xD200xD20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_60xD240xDFF0xE000xE00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_70xE040xE04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_70xE080xE08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_70xE0C0xE0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_70xE100xE10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_70xE140xE14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_70xE180xE18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_70xE1C0xE1F0xE200xE20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_70xE240xEFF0xF000xF00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_70xF040xF04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_70xF080xF08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_70xF0C0xF0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_70xF100xF10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_70xF140xF14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_70xF180xF18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_70xF1C0xF1F0xF200xF20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_70xF240xFFF0x10000x1000DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_80x10040x1004DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_80x10080x1008DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_80x100C0x100CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_80x10100x1010DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_80x10140x1014DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_80x10180x1018DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_80x101C0x101F0x10200x1020DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_80x10240x10FF0x11000x1100DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_80x11040x1104DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_80x11080x1108DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_80x110C0x110CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_80x11100x1110DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_80x11140x1114DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_80x11180x1118DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_80x111C0x111F0x11200x1120DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_80x11240x11FF0x12000x1200DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_90x12040x1204DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_90x12080x1208DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_90x120C0x120CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_90x12100x1210DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_90x12140x1214DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_90x12180x1218DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_90x121C0x121F0x12200x1220DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_90x12240x12FF0x13000x1300DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_90x13040x1304DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_90x13080x1308DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_90x130C0x130CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_90x13100x1310DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_90x13140x1314DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_90x13180x1318DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_90x131C0x131F0x13200x1320DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_90x13240x13FF0x14000x1400DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_100x14040x1404DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_100x14080x1408DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_100x140C0x140CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_100x14100x1410DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_100x14140x1414DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_100x14180x1418DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_100x141C0x141F0x14200x1420DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_100x14240x14FF0x15000x1500DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_100x15040x1504DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_100x15080x1508DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_100x150C0x150CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_100x15100x1510DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_100x15140x1514DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_100x15180x1518DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_100x151C0x151F0x15200x1520DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_100x15240x15FF0x16000x1600DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_110x16040x1604DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_110x16080x1608DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_110x160C0x160CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_110x16100x1610DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_110x16140x1614DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_110x16180x1618DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_110x161C0x161F0x16200x1620DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_110x16240x16FF0x17000x1700DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_110x17040x1704DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_110x17080x1708DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_110x170C0x170CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_110x17100x1710DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_110x17140x1714DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_110x17180x1718DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_110x171C0x171F0x17200x1720DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_110x17240x17FF0x18000x1800DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_120x18040x1804DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_120x18080x1808DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_120x180C0x180CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_120x18100x1810DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_120x18140x1814DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_120x18180x1818DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_120x181C0x181F0x18200x1820DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_120x18240x18FF0x19000x1900DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_120x19040x1904DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_120x19080x1908DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_120x190C0x190CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_120x19100x1910DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_120x19140x1914DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_120x19180x1918DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_120x191C0x191F0x19200x1920DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_120x19240x19FF0x1A000x1A00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_130x1A040x1A04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_130x1A080x1A08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_130x1A0C0x1A0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_130x1A100x1A10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_130x1A140x1A14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_130x1A180x1A18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_130x1A1C0x1A1F0x1A200x1A20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_130x1A240x1AFF0x1B000x1B00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_130x1B040x1B04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_130x1B080x1B08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_130x1B0C0x1B0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_130x1B100x1B10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_130x1B140x1B14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_130x1B180x1B18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_130x1B1C0x1B1F0x1B200x1B20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_130x1B240x1BFF0x1C000x1C00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_140x1C040x1C04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_140x1C080x1C08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_140x1C0C0x1C0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_140x1C100x1C10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_140x1C140x1C14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_140x1C180x1C18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_140x1C1C0x1C1F0x1C200x1C20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_140x1C240x1CFF0x1D000x1D00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_140x1D040x1D04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_140x1D080x1D08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_140x1D0C0x1D0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_140x1D100x1D10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_140x1D140x1D14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_140x1D180x1D18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_140x1D1C0x1D1F0x1D200x1D20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_140x1D240x1DFF0x1E000x1E00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_150x1E040x1E04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_150x1E080x1E08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_150x1E0C0x1E0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_150x1E100x1E10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_150x1E140x1E14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_150x1E180x1E18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_150x1E1C0x1E1F0x1E200x1E20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_150x1E240x1EFF0x1F000x1F00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_150x1F040x1F04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_150x1F080x1F08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_150x1F0C0x1F0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_150x1F100x1F10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_150x1F140x1F14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_150x1F180x1F18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_150x1F1C0x1F1F0x1F200x1F20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_150x1F240x20FF0x21000x2100DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_16PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_160x21040x2104DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_16PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_160x21080x2108DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_16PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_160x210C0x210CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_16PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_160x21100x2110DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_16PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_160x21140x2114DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_16PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_160x21180x2118DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_160x211C0x211F0x21200x2120DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_160x21240x22FF0x23000x2300DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_17PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_170x23040x2304DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_17PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_170x23080x2308DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_17PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_170x230C0x230CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_17PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_170x23100x2310DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_17PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_170x23140x2314DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_17PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_170x23180x2318DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_170x231C0x231F0x23200x2320DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_170x23240x24FF0x25000x2500DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_18PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_180x25040x2504DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_18PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_180x25080x2508DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_18PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_180x250C0x250CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_18PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_180x25100x2510DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_18PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_180x25140x2514DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_18PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_180x25180x2518DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_180x251C0x251F0x25200x2520DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_180x25240x26FF0x27000x2700DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_19PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_190x27040x2704DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_19PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_190x27080x2708DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_19PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_190x270C0x270CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_19PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_190x27100x2710DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_19PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_190x27140x2714DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_19PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_190x27180x2718DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_190x271C0x271F0x27200x2720DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_190x27240x28FF0x29000x2900DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_20PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_200x29040x2904DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_20PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_200x29080x2908DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_20PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_200x290C0x290CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_20PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_200x29100x2910DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_20PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_200x29140x2914DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_20PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_200x29180x2918DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_200x291C0x291F0x29200x2920DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_200x29240x2AFF0x2B000x2B00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_21PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_210x2B040x2B04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_21PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_210x2B080x2B08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_21PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_210x2B0C0x2B0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_21PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_210x2B100x2B10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_21PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_210x2B140x2B14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_21PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_210x2B180x2B18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_210x2B1C0x2B1F0x2B200x2B20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_210x2B240x2CFF0x2D000x2D00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_22PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_220x2D040x2D04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_22PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_220x2D080x2D08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_22PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_220x2D0C0x2D0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_22PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_220x2D100x2D10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_22PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_220x2D140x2D14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_22PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_220x2D180x2D18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_220x2D1C0x2D1F0x2D200x2D20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_220x2D240x2EFF0x2F000x2F00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_23PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_230x2F040x2F04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_23PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_230x2F080x2F08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_23PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_230x2F0C0x2F0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_23PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_230x2F100x2F10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_23PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_230x2F140x2F14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_23PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_230x2F180x2F18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_230x2F1C0x2F1F0x2F200x2F20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_230x2F240x30FF0x31000x3100DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_24PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_240x31040x3104DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_24PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_240x31080x3108DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_24PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_240x310C0x310CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_24PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_240x31100x3110DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_24PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_240x31140x3114DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_24PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_240x31180x3118DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_240x311C0x311F0x31200x3120DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_240x31240x32FF0x33000x3300DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_25PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_250x33040x3304DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_25PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_250x33080x3308DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_25PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_250x330C0x330CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_25PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_250x33100x3310DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_25PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_250x33140x3314DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_25PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_250x33180x3318DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_250x331C0x331F0x33200x3320DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_250x33240x34FF0x35000x3500DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_26PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_260x35040x3504DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_26PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_260x35080x3508DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_26PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_260x350C0x350CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_26PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_260x35100x3510DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_26PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_260x35140x3514DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_26PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_260x35180x3518DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_260x351C0x351F0x35200x3520DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_260x35240x36FF0x37000x3700DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_27PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_270x37040x3704DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_27PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_270x37080x3708DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_27PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_270x370C0x370CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_27PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_270x37100x3710DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_27PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_270x37140x3714DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_27PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_270x37180x3718DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_270x371C0x371F0x37200x3720DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_270x37240x38FF0x39000x3900DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_28PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_280x39040x3904DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_28PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_280x39080x3908DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_28PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_280x390C0x390CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_28PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_280x39100x3910DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_28PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_280x39140x3914DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_28PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_280x39180x3918DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_280x391C0x391F0x39200x3920DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_280x39240x3AFF0x3B000x3B00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_29PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_290x3B040x3B04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_29PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_290x3B080x3B08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_29PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_290x3B0C0x3B0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_29PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_290x3B100x3B10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_29PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_290x3B140x3B14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_29PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_290x3B180x3B18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_290x3B1C0x3B1F0x3B200x3B20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_290x3B240x3CFF0x3D000x3D00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_30PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_300x3D040x3D04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_30PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_300x3D080x3D08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_30PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_300x3D0C0x3D0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_30PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_300x3D100x3D10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_30PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_300x3D140x3D14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_30PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_300x3D180x3D18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_300x3D1C0x3D1F0x3D200x3D20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_300x3D240x3EFF0x3F000x3F00DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_31PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_310x3F040x3F04DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_31PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_310x3F080x3F08DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_31PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_310x3F0C0x3F0CDBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_31PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_310x3F100x3F10DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_31PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_310x3F140x3F14DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_31PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_310x3F180x3F18DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_310x3F1C0x3F1F0x3F200x3F20DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31PE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_310x3F240x1FF230x1FF240x7FFFF0x800000x81123DBI_Slave.PF0_DMA_CAPPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP0x800000x80000DBI_Slave.PF0_DMA_CAP.DMA_CTRL_DATA_ARB_PRIOR_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CTRL_DATA_ARB_PRIOR_OFF0x800040x800070x800080x80008DBI_Slave.PF0_DMA_CAP.DMA_CTRL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CTRL_OFF0x8000C0x8000CDBI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_EN_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_EN_OFF0x800100x80010DBI_Slave.PF0_DMA_CAP.DMA_WRITE_DOORBELL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_DOORBELL_OFF0x800140x800170x800180x80018DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF0x8001C0x8001CDBI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF0x800200x8002B0x8002C0x8002CDBI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_EN_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_EN_OFF0x800300x80030DBI_Slave.PF0_DMA_CAP.DMA_READ_DOORBELL_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_DOORBELL_OFF0x800340x800370x800380x80038DBI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF0x8003C0x8003CDBI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF0x800400x8004B0x8004C0x8004CDBI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_STATUS_OFF0x800500x800530x800540x80054DBI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_MASK_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_MASK_OFF0x800580x80058DBI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_CLEAR_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_CLEAR_OFF0x8005C0x8005CDBI_Slave.PF0_DMA_CAP.DMA_WRITE_ERR_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ERR_STATUS_OFF0x800600x80060DBI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_LOW_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_LOW_OFF0x800640x80064DBI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_HIGH_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_HIGH_OFF0x800680x80068DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_LOW_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_LOW_OFF0x8006C0x8006CDBI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_HIGH_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_HIGH_OFF0x800700x80070DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH01_IMWR_DATA_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH01_IMWR_DATA_OFF0x800740x80074DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH23_IMWR_DATA_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH23_IMWR_DATA_OFF0x800780x80078DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH45_IMWR_DATA_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH45_IMWR_DATA_OFF0x8007C0x8007CDBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH67_IMWR_DATA_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH67_IMWR_DATA_OFF0x800800x8008F0x800900x80090DBI_Slave.PF0_DMA_CAP.DMA_WRITE_LINKED_LIST_ERR_EN_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_LINKED_LIST_ERR_EN_OFF0x800940x8009F0x800A00x800A0DBI_Slave.PF0_DMA_CAP.DMA_READ_INT_STATUS_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_INT_STATUS_OFF0x800A40x800A70x800A80x800A8DBI_Slave.PF0_DMA_CAP.DMA_READ_INT_MASK_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_INT_MASK_OFF0x800AC0x800ACDBI_Slave.PF0_DMA_CAP.DMA_READ_INT_CLEAR_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_INT_CLEAR_OFF0x800B00x800B30x800B40x800B4DBI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_LOW_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_LOW_OFF0x800B80x800B8DBI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_HIGH_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_HIGH_OFF0x800BC0x800C30x800C40x800C4DBI_Slave.PF0_DMA_CAP.DMA_READ_LINKED_LIST_ERR_EN_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_LINKED_LIST_ERR_EN_OFF0x800C80x800CB0x800CC0x800CCDBI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_LOW_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_LOW_OFF0x800D00x800D0DBI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_HIGH_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_HIGH_OFF0x800D40x800D4DBI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_LOW_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_LOW_OFF0x800D80x800D8DBI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_HIGH_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_HIGH_OFF0x800DC0x800DCDBI_Slave.PF0_DMA_CAP.DMA_READ_CH01_IMWR_DATA_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CH01_IMWR_DATA_OFF0x800E00x800E0DBI_Slave.PF0_DMA_CAP.DMA_READ_CH23_IMWR_DATA_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CH23_IMWR_DATA_OFF0x800E40x800E4DBI_Slave.PF0_DMA_CAP.DMA_READ_CH45_IMWR_DATA_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CH45_IMWR_DATA_OFF0x800E80x800E8DBI_Slave.PF0_DMA_CAP.DMA_READ_CH67_IMWR_DATA_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CH67_IMWR_DATA_OFF0x800EC0x801070x801080x80108DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF0x8010C0x8010CDBI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF0x801100x801170x801180x80118DBI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF0x8011C0x8011CDBI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFFPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF0x801200x801FF0x802000x80200DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_00x802040x80204DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_00x802080x80208DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_00x8020C0x8020CDBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_00x802100x80210DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_00x802140x80214DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_00x802180x80218DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_00x8021C0x8021CDBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_00x802200x80220DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_00x802240x802FF0x803000x80300DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_00x803040x80304DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_00x803080x80308DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_00x8030C0x8030CDBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_00x803100x80310DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_00x803140x80314DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_00x803180x80318DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_00x8031C0x8031CDBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_00x803200x80320DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_0PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_00x803240x803FF0x804000x80400DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_10x804040x80404DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_10x804080x80408DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_10x8040C0x8040CDBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_10x804100x80410DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_10x804140x80414DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_10x804180x80418DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_10x8041C0x8041CDBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_10x804200x80420DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_10x804240x804FF0x805000x80500DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_10x805040x80504DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_10x805080x80508DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_10x8050C0x8050CDBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_10x805100x80510DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_10x805140x80514DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_10x805180x80518DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_10x8051C0x8051CDBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_10x805200x80520DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_1PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_10x805240x805FF0x806000x80600DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_20x806040x80604DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_20x806080x80608DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_20x8060C0x8060CDBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_20x806100x80610DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_20x806140x80614DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_20x806180x80618DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_20x8061C0x8061CDBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_20x806200x80620DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_20x806240x806FF0x807000x80700DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_20x807040x80704DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_20x807080x80708DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_20x8070C0x8070CDBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_20x807100x80710DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_20x807140x80714DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_20x807180x80718DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_20x8071C0x8071CDBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_20x807200x80720DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_2PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_20x807240x807FF0x808000x80800DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_30x808040x80804DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_30x808080x80808DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_30x8080C0x8080CDBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_30x808100x80810DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_30x808140x80814DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_30x808180x80818DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_30x8081C0x8081CDBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_30x808200x80820DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_30x808240x808FF0x809000x80900DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_30x809040x80904DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_30x809080x80908DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_30x8090C0x8090CDBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_30x809100x80910DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_30x809140x80914DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_30x809180x80918DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_30x8091C0x8091CDBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_30x809200x80920DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_3PE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_30x809240x81123groupPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAPPF0_ATU_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr579700x0R/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAPATU Por Logic StructureregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_0IATU_REGION_CTRL_1_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr322800x0R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32191When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32202When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32211This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32222When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32234When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32246Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32259When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32279Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_0IATU_REGION_CTRL_2_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr324880x4R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32301MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32313TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32333TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSB2BITS_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32345TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32358Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32370Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32393TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32410Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32431Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32445DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32465CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32477Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32487Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr325250x8R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32513Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32524Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr325410xCR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32540Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_0IATU_LIMIT_ADDR_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr325680x10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32557Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32567Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr325970x14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32596When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr326110x18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32610Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr326430x20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32630Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32642Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_0IATU_REGION_CTRL_1_OFF_INBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr327560x100R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32657When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32670When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32683When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32696When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32709When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32721Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32735When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32755Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_0IATU_REGION_CTRL_2_OFF_INBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr330510x104R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32781MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32806BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32824Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32835TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32846TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32858ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32871TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32885Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32904Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32917PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32933Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32949Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32968Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32983CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr32995Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33040Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33050Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_0IATU_LWR_BASE_ADDR_OFF_INBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr330880x108R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33076Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33087Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_0IATU_UPPER_BASE_ADDR_OFF_INBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr331020x10CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33101Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_0IATU_LIMIT_ADDR_OFF_INBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr331290x110R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33118Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33128Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_0IATU_LWR_TARGET_ADDR_OFF_INBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr331680x114R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33154Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33167Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr331840x118R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33183Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr332160x120R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33203Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33215Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_1IATU_REGION_CTRL_1_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr333190x200R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33230When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33241When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33250This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33261When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33273When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33285Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33298When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33318Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_1IATU_REGION_CTRL_2_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr335270x204R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33340MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33352TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33372TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSB2BITS_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33384TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33397Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33409Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33432TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33449Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33470Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33484DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33504CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33516Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33526Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr335640x208R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33552Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33563Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr335800x20CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33579Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_1IATU_LIMIT_ADDR_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr336070x210R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33596Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33606Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr336360x214R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33635When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr336500x218R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33649Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr336820x220R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33669Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33681Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_1IATU_REGION_CTRL_1_OFF_INBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr337950x300R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33696When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33709When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33722When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33735When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33748When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33760Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33774When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33794Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_1IATU_REGION_CTRL_2_OFF_INBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr340900x304R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33820MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33845BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33863Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33874TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33885TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33897ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33910TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33924Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33943Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33956PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33972Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr33988Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34007Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34022CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34034Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34079Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34089Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_1IATU_LWR_BASE_ADDR_OFF_INBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr341270x308R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34115Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34126Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_1IATU_UPPER_BASE_ADDR_OFF_INBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr341410x30CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34140Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_1IATU_LIMIT_ADDR_OFF_INBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr341680x310R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34157Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34167Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_1IATU_LWR_TARGET_ADDR_OFF_INBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr342070x314R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34193Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34206Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr342230x318R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34222Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr342550x320R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34242Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34254Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_2IATU_REGION_CTRL_1_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr343580x400R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34269When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34280When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34289This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34300When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34312When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34324Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34337When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34357Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_2IATU_REGION_CTRL_2_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr345660x404R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34379MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34391TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34411TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSB2BITS_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34423TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34436Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34448Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34471TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34488Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34509Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34523DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34543CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34555Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34565Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr346030x408R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34591Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34602Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr346190x40CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34618Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_2IATU_LIMIT_ADDR_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr346460x410R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34635Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34645Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr346750x414R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34674When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr346890x418R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34688Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr347210x420R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34708Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34720Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_2IATU_REGION_CTRL_1_OFF_INBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr348340x500R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34735When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34748When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34761When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34774When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34787When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34799Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34813When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34833Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_2IATU_REGION_CTRL_2_OFF_INBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr351290x504R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34859MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34884BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34902Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34913TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34924TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34936ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34949TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34963Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34982Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr34995PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35011Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35027Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35046Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35061CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35073Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35118Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35128Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_2IATU_LWR_BASE_ADDR_OFF_INBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr351660x508R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35154Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35165Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_2IATU_UPPER_BASE_ADDR_OFF_INBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr351800x50CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35179Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_2IATU_LIMIT_ADDR_OFF_INBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr352070x510R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35196Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35206Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_2IATU_LWR_TARGET_ADDR_OFF_INBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr352460x514R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35232Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35245Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr352620x518R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35261Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr352940x520R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35281Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35293Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_3IATU_REGION_CTRL_1_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr353970x600R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35308When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35319When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35328This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35339When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35351When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35363Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35376When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35396Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_3IATU_REGION_CTRL_2_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr356050x604R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35418MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35430TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35450TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSB2BITS_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35462TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35475Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35487Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35510TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35527Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35548Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35562DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35582CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35594Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35604Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr356420x608R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35630Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35641Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr356580x60CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35657Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_3IATU_LIMIT_ADDR_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr356850x610R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35674Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35684Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr357140x614R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35713When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr357280x618R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35727Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr357600x620R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35747Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35759Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_3IATU_REGION_CTRL_1_OFF_INBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr358730x700R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35774When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35787When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35800When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35813When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35826When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35838Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35852When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35872Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_3IATU_REGION_CTRL_2_OFF_INBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr361680x704R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35898MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35923BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35941Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35952TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35963TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35975ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr35988TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36002Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36021Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36034PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36050Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36066Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36085Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36100CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36112Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36157Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36167Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_3IATU_LWR_BASE_ADDR_OFF_INBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr362050x708R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36193Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36204Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_3IATU_UPPER_BASE_ADDR_OFF_INBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr362190x70CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36218Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_3IATU_LIMIT_ADDR_OFF_INBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr362460x710R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36235Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36245Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_3IATU_LWR_TARGET_ADDR_OFF_INBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr362850x714R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36271Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36284Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr363010x718R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36300Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr363330x720R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36320Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36332Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_4IATU_REGION_CTRL_1_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr364360x800R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36347When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36358When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36367This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36378When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36390When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36402Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36415When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36435Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_4IATU_REGION_CTRL_2_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr366440x804R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36457MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36469TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36489TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSB2BITS_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36501TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36514Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36526Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36549TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36566Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36587Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36601DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36621CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36633Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36643Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr366810x808R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36669Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36680Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr366970x80CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36696Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_4IATU_LIMIT_ADDR_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr367240x810R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36713Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36723Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr367530x814R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36752When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr367670x818R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36766Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr367990x820R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36786Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36798Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_4IATU_REGION_CTRL_1_OFF_INBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr369120x900R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36813When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36826When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36839When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36852When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36865When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36877Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36891When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36911Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_4IATU_REGION_CTRL_2_OFF_INBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr372070x904R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36937MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36962BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36980Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr36991TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37002TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37014ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37027TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37041Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37060Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37073PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37089Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37105Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37124Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37139CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37151Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37196Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37206Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_4IATU_LWR_BASE_ADDR_OFF_INBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr372440x908R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37232Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37243Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_4IATU_UPPER_BASE_ADDR_OFF_INBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr372580x90CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37257Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_4IATU_LIMIT_ADDR_OFF_INBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr372850x910R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37274Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37284Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_4IATU_LWR_TARGET_ADDR_OFF_INBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr373240x914R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37310Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37323Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr373400x918R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37339Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr373720x920R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37359Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37371Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_5IATU_REGION_CTRL_1_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr374750xA00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37386When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37397When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37406This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37417When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37429When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37441Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37454When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37474Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_5IATU_REGION_CTRL_2_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr376830xA04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37496MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37508TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37528TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSB2BITS_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37540TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37553Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37565Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37588TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37605Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37626Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37640DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37660CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37672Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37682Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr377200xA08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37708Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37719Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr377360xA0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37735Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_5IATU_LIMIT_ADDR_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr377630xA10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37752Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37762Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr377920xA14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37791When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr378060xA18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37805Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr378380xA20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37825Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37837Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_5IATU_REGION_CTRL_1_OFF_INBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr379510xB00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37852When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37865When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37878When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37891When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37904When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37916Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37930When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37950Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_5IATU_REGION_CTRL_2_OFF_INBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr382460xB04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr37976MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38001BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38019Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38030TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38041TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38053ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38066TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38080Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38099Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38112PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38128Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38144Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38163Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38178CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38190Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38235Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38245Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_5IATU_LWR_BASE_ADDR_OFF_INBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr382830xB08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38271Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38282Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_5IATU_UPPER_BASE_ADDR_OFF_INBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr382970xB0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38296Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_5IATU_LIMIT_ADDR_OFF_INBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr383240xB10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38313Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38323Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_5IATU_LWR_TARGET_ADDR_OFF_INBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr383630xB14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38349Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38362Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr383790xB18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38378Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr384110xB20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38398Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38410Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_6IATU_REGION_CTRL_1_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr385140xC00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38425When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38436When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38445This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38456When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38468When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38480Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38493When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38513Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_6IATU_REGION_CTRL_2_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr387220xC04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38535MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38547TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38567TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSB2BITS_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38579TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38592Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38604Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38627TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38644Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38665Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38679DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38699CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38711Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38721Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr387590xC08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38747Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38758Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr387750xC0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38774Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_6IATU_LIMIT_ADDR_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr388020xC10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38791Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38801Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr388310xC14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38830When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr388450xC18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38844Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr388770xC20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38864Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38876Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_6IATU_REGION_CTRL_1_OFF_INBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr389900xD00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38891When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38904When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38917When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38930When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38943When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38955Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38969When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr38989Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_6IATU_REGION_CTRL_2_OFF_INBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr392850xD04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39015MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39040BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39058Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39069TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39080TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39092ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39105TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39119Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39138Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39151PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39167Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39183Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39202Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39217CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39229Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39274Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39284Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_6IATU_LWR_BASE_ADDR_OFF_INBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr393220xD08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39310Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39321Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_6IATU_UPPER_BASE_ADDR_OFF_INBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr393360xD0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39335Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_6IATU_LIMIT_ADDR_OFF_INBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr393630xD10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39352Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39362Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_6IATU_LWR_TARGET_ADDR_OFF_INBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr394020xD14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39388Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39401Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr394180xD18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39417Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr394500xD20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39437Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39449Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_7IATU_REGION_CTRL_1_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr395530xE00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39464When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39475When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39484This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39495When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39507When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39519Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39532When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39552Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_7IATU_REGION_CTRL_2_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr397610xE04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39574MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39586TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39606TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSB2BITS_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39618TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39631Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39643Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39666TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39683Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39704Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39718DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39738CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39750Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39760Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr397980xE08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39786Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39797Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr398140xE0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39813Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_7IATU_LIMIT_ADDR_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr398410xE10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39830Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39840Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr398700xE14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39869When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr398840xE18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39883Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr399160xE20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39903Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39915Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_7IATU_REGION_CTRL_1_OFF_INBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr400290xF00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39930When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39943When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39956When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39969When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39982When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr39994Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40008When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40028Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_7IATU_REGION_CTRL_2_OFF_INBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr403240xF04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40054MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40079BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40097Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40108TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40119TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40131ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40144TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40158Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40177Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40190PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40206Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40222Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40241Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40256CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40268Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40313Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40323Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_7IATU_LWR_BASE_ADDR_OFF_INBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr403610xF08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40349Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40360Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_7IATU_UPPER_BASE_ADDR_OFF_INBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr403750xF0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40374Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_7IATU_LIMIT_ADDR_OFF_INBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr404020xF10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40391Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40401Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_7IATU_LWR_TARGET_ADDR_OFF_INBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr404410xF14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40427Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40440Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr404570xF18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40456Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr404890xF20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40476Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40488Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_8IATU_REGION_CTRL_1_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr405920x1000R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40503When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40514When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40523This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40534When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40546When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40558Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40571When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_8_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40591Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_8IATU_REGION_CTRL_2_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr408000x1004R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40613MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40625TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TAG_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40645TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_MSB2BITS_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40657TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_FUNC_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40670Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_SNP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40682Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40705TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INHIBIT_PAYLOAD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40722Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_HEADER_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40743Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_DMA_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40757DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40777CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40789Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_8_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40799Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr408370x1008R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40825Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40836Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr408530x100CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40852Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_8IATU_LIMIT_ADDR_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr408800x1010R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40869Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_8_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40879Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr409090x1014R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40908When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr409230x1018R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40922Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr409550x1020R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40942Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_8_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40954Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_8IATU_REGION_CTRL_1_OFF_INBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr410680x1100R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40969When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40982When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr40995When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41008When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41021When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41033Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41047When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_8_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41067Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_8IATU_REGION_CTRL_2_OFF_INBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr413630x1104R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41093MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41118BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41136Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41147TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41158TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41170ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41183TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41197Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41216Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41229PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41245Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41261Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41280Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41295CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41307Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41352Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_8_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41362Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_8IATU_LWR_BASE_ADDR_OFF_INBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr414000x1108R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41388Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_8_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41399Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_8IATU_UPPER_BASE_ADDR_OFF_INBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr414140x110CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_8_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41413Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_8IATU_LIMIT_ADDR_OFF_INBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr414410x1110R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41430Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_8_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41440Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_8IATU_LWR_TARGET_ADDR_OFF_INBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr414800x1114R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41466Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_8_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41479Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr414960x1118R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_8_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41495Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr415280x1120R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41515Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_8_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41527Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_9IATU_REGION_CTRL_1_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr416310x1200R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41542When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41553When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41562This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41573When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41585When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41597Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41610When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_9_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41630Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_9IATU_REGION_CTRL_2_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr418390x1204R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41652MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41664TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TAG_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41684TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_MSB2BITS_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41696TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_FUNC_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41709Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_SNP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41721Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41744TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INHIBIT_PAYLOAD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41761Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_HEADER_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41782Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_DMA_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41796DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41816CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41828Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_9_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41838Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr418760x1208R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41864Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41875Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr418920x120CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41891Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_9IATU_LIMIT_ADDR_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr419190x1210R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41908Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_9_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41918Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr419480x1214R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41947When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr419620x1218R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41961Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr419940x1220R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41981Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_9_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr41993Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_9IATU_REGION_CTRL_1_OFF_INBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr421070x1300R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42008When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42021When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42034When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42047When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42060When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42072Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42086When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_9_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42106Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_9IATU_REGION_CTRL_2_OFF_INBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr424020x1304R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42132MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42157BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42175Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42186TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42197TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42209ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42222TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42236Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42255Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42268PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42284Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42300Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42319Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42334CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42346Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42391Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_9_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42401Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_9IATU_LWR_BASE_ADDR_OFF_INBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr424390x1308R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42427Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_9_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42438Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_9IATU_UPPER_BASE_ADDR_OFF_INBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr424530x130CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_9_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42452Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_9IATU_LIMIT_ADDR_OFF_INBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr424800x1310R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42469Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_9_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42479Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_9IATU_LWR_TARGET_ADDR_OFF_INBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr425190x1314R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42505Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_9_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42518Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr425350x1318R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_9_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42534Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr425670x1320R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42554Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_9_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42566Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_10IATU_REGION_CTRL_1_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr426700x1400R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42581When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42592When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42601This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42612When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42624When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42636Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42649When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_10_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42669Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_10IATU_REGION_CTRL_2_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr428780x1404R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42691MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42703TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TAG_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42723TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_MSB2BITS_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42735TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_FUNC_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42748Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_SNP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42760Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42783TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INHIBIT_PAYLOAD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42800Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_HEADER_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42821Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_DMA_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42835DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42855CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42867Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_10_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42877Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr429150x1408R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42903Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42914Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr429310x140CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42930Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_10IATU_LIMIT_ADDR_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr429580x1410R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42947Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_10_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42957Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr429870x1414R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr42986When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr430010x1418R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43000Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr430330x1420R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43020Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_10_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43032Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_10IATU_REGION_CTRL_1_OFF_INBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr431460x1500R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43047When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43060When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43073When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43086When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43099When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43111Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43125When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_10_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43145Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_10IATU_REGION_CTRL_2_OFF_INBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr434410x1504R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43171MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43196BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43214Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43225TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43236TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43248ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43261TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43275Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43294Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43307PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43323Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43339Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43358Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43373CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43385Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43430Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_10_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43440Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_10IATU_LWR_BASE_ADDR_OFF_INBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr434780x1508R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43466Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_10_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43477Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_10IATU_UPPER_BASE_ADDR_OFF_INBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr434920x150CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_10_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43491Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_10IATU_LIMIT_ADDR_OFF_INBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr435190x1510R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43508Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_10_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43518Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_10IATU_LWR_TARGET_ADDR_OFF_INBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr435580x1514R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43544Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_10_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43557Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr435740x1518R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_10_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43573Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr436060x1520R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43593Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_10_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43605Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_11IATU_REGION_CTRL_1_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr437090x1600R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43620When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43631When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43640This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43651When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43663When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43675Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43688When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_11_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43708Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_11IATU_REGION_CTRL_2_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr439170x1604R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43730MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43742TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TAG_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43762TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_MSB2BITS_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43774TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_FUNC_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43787Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_SNP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43799Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43822TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INHIBIT_PAYLOAD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43839Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_HEADER_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43860Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_DMA_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43874DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43894CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43906Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_11_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43916Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr439540x1608R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43942Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43953Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr439700x160CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43969Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_11IATU_LIMIT_ADDR_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr439970x1610R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43986Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_11_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr43996Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr440260x1614R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44025When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr440400x1618R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44039Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr440720x1620R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44059Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_11_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44071Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_11IATU_REGION_CTRL_1_OFF_INBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr441850x1700R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44086When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44099When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44112When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44125When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44138When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44150Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44164When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_11_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44184Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_11IATU_REGION_CTRL_2_OFF_INBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr444800x1704R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44210MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44235BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44253Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44264TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44275TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44287ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44300TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44314Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44333Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44346PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44362Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44378Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44397Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44412CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44424Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44469Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_11_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44479Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_11IATU_LWR_BASE_ADDR_OFF_INBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr445170x1708R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44505Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_11_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44516Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_11IATU_UPPER_BASE_ADDR_OFF_INBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr445310x170CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_11_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44530Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_11IATU_LIMIT_ADDR_OFF_INBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr445580x1710R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44547Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_11_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44557Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_11IATU_LWR_TARGET_ADDR_OFF_INBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr445970x1714R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44583Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_11_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44596Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr446130x1718R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_11_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44612Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr446450x1720R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44632Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_11_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44644Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_12IATU_REGION_CTRL_1_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr447480x1800R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44659When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44670When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44679This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44690When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44702When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44714Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44727When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_12_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44747Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_12IATU_REGION_CTRL_2_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr449560x1804R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44769MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44781TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TAG_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44801TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_MSB2BITS_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44813TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_FUNC_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44826Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_SNP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44838Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44861TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INHIBIT_PAYLOAD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44878Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_HEADER_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44899Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_DMA_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44913DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44933CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44945Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_12_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44955Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr449930x1808R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44981Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr44992Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr450090x180CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45008Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_12IATU_LIMIT_ADDR_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr450360x1810R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45025Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_12_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45035Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr450650x1814R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45064When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr450790x1818R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45078Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr451110x1820R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45098Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_12_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45110Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_12IATU_REGION_CTRL_1_OFF_INBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr452240x1900R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45125When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45138When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45151When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45164When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45177When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45189Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45203When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_12_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45223Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_12IATU_REGION_CTRL_2_OFF_INBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr455190x1904R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45249MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45274BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45292Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45303TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45314TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45326ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45339TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45353Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45372Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45385PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45401Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45417Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45436Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45451CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45463Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45508Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_12_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45518Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_12IATU_LWR_BASE_ADDR_OFF_INBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr455560x1908R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45544Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_12_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45555Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_12IATU_UPPER_BASE_ADDR_OFF_INBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr455700x190CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_12_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45569Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_12IATU_LIMIT_ADDR_OFF_INBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr455970x1910R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45586Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_12_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45596Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_12IATU_LWR_TARGET_ADDR_OFF_INBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr456360x1914R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45622Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_12_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45635Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr456520x1918R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_12_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45651Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr456840x1920R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45671Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_12_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45683Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_13IATU_REGION_CTRL_1_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr457870x1A00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45698When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45709When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45718This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45729When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45741When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45753Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45766When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_13_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45786Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_13IATU_REGION_CTRL_2_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr459950x1A04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45808MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45820TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TAG_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45840TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_MSB2BITS_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45852TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_FUNC_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45865Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_SNP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45877Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45900TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INHIBIT_PAYLOAD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45917Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_HEADER_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45938Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_DMA_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45952DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45972CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45984Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_13_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr45994Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr460320x1A08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46020Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46031Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr460480x1A0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46047Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_13IATU_LIMIT_ADDR_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr460750x1A10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46064Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_13_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46074Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr461040x1A14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46103When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr461180x1A18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46117Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr461500x1A20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46137Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_13_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46149Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_13IATU_REGION_CTRL_1_OFF_INBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr462630x1B00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46164When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46177When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46190When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46203When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46216When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46228Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46242When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_13_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46262Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_13IATU_REGION_CTRL_2_OFF_INBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr465580x1B04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46288MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46313BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46331Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46342TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46353TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46365ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46378TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46392Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46411Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46424PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46440Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46456Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46475Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46490CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46502Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46547Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_13_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46557Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_13IATU_LWR_BASE_ADDR_OFF_INBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr465950x1B08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46583Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_13_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46594Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_13IATU_UPPER_BASE_ADDR_OFF_INBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr466090x1B0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_13_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46608Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_13IATU_LIMIT_ADDR_OFF_INBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr466360x1B10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46625Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_13_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46635Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_13IATU_LWR_TARGET_ADDR_OFF_INBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr466750x1B14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46661Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_13_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46674Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr466910x1B18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_13_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46690Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr467230x1B20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46710Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_13_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46722Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_14IATU_REGION_CTRL_1_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr468260x1C00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46737When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46748When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46757This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46768When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46780When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46792Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46805When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_14_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46825Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_14IATU_REGION_CTRL_2_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr470340x1C04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46847MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46859TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TAG_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46879TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_MSB2BITS_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46891TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_FUNC_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46904Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_SNP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46916Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46939TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INHIBIT_PAYLOAD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46956Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_HEADER_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46977Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_DMA_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr46991DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47011CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47023Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_14_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47033Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr470710x1C08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47059Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47070Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr470870x1C0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47086Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_14IATU_LIMIT_ADDR_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr471140x1C10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47103Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_14_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47113Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr471430x1C14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47142When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr471570x1C18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47156Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr471890x1C20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47176Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_14_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47188Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_14IATU_REGION_CTRL_1_OFF_INBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr473020x1D00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47203When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47216When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47229When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47242When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47255When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47267Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47281When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_14_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47301Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_14IATU_REGION_CTRL_2_OFF_INBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr475970x1D04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47327MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47352BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47370Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47381TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47392TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47404ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47417TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47431Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47450Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47463PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47479Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47495Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47514Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47529CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47541Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47586Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_14_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47596Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_14IATU_LWR_BASE_ADDR_OFF_INBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr476340x1D08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47622Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_14_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47633Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_14IATU_UPPER_BASE_ADDR_OFF_INBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr476480x1D0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_14_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47647Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_14IATU_LIMIT_ADDR_OFF_INBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr476750x1D10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47664Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_14_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47674Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_14IATU_LWR_TARGET_ADDR_OFF_INBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr477140x1D14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47700Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_14_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47713Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr477300x1D18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_14_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47729Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr477620x1D20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47749Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_14_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47761Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_OUTBOUND_15IATU_REGION_CTRL_1_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr478650x1E00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47776When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47787When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47796This is a reserved field. Do not use.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47807When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47819When the address of an outbound TLP is matched to this region, then the TH field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47831Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47844When the address of an outbound TLP is matched to this region, then the PH field of the TLP is changed to the value in this register. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_OUTBOUND_15_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47864Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_OUTBOUND_15IATU_REGION_CTRL_2_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr480730x1E04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47886MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.Memory TLPs: (ST;Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WTAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47898TAG.The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.Note: This register field is sticky.1580x00R/WTAG_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TAG_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47918TAG Substitute Enable.When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.Note: This register field is sticky.16160x0R/WMSB2BITS_TAGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_MSB2BITS_TAG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47930TAG.Two most significant bits of the substituted TAG field in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky.18170x0R/WFUNC_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_FUNC_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47943Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."Note: This register field is sticky.19190x0R/WSNPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_SNP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47955Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.Note: This register field is sticky.20200x0R/WTLP_HEADER_FIELDS_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_TLP_HEADER_FIELDS_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47978TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).Note: This register field is sticky. Note: This register field is sticky.21210x0R/WINHIBIT_PAYLOADPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INHIBIT_PAYLOAD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr47995Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data.When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be sent. Note: This register field is sticky.22220x0R/WHEADER_SUBSTITUTE_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_HEADER_SUBSTITUTE_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48016Header Substitute Enable.When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region.Note: This register field is sticky.23230x0R/W--26240x0rDMA_BYPASSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_DMA_BYPASS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48030DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.Note: This field is reserved for the SW product. You must set it to '0'.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48050CFG Shift Mode.The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48062Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/W--30300x0rREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_OUTBOUND_15_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48072Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr481100x1E08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48098Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48109Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr481260x1E0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48125Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_OUTBOUND_15IATU_LIMIT_ADDR_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr481530x1E10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48142Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_OUTBOUND_15_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48152Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr481820x1E14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_RW_OUTBOUNDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15_LWR_TARGET_RW_OUTBOUND_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48181When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE).When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr481960x1E18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48195Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr482280x1E20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48215Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_15_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48227Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_15IATU_REGION_CTRL_1_OFF_INBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr483410x1F00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48242When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48255When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48268When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48281When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48294When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48306Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48320When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_15_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48340Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_15IATU_REGION_CTRL_2_OFF_INBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr486360x1F04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48366MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48391BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48409Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48420TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48431TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48443ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48456TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48470Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48489Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48502PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48518Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48534Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48553Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48568CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48580Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48625Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_15_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48635Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_15IATU_LWR_BASE_ADDR_OFF_INBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr486730x1F08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48661Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_15_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48672Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_15IATU_UPPER_BASE_ADDR_OFF_INBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr486870x1F0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_15_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48686Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_15IATU_LIMIT_ADDR_OFF_INBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr487140x1F10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48703Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_15_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48713Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_15IATU_LWR_TARGET_ADDR_OFF_INBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr487530x1F14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48739Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_15_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48752Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr487690x1F18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_15_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48768Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr488010x1F20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48788Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_15_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48800Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_16IATU_REGION_CTRL_1_OFF_INBOUND_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr489140x2100R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48815When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48828When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48841When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48854When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48867When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48879Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48893When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_16_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48913Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_16IATU_REGION_CTRL_2_OFF_INBOUND_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr492090x2104R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48939MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48964BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48982Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr48993TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49004TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49016ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49029TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49043Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49062Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49075PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49091Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49107Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49126Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49141CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49153Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49198Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_16_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49208Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_16IATU_LWR_BASE_ADDR_OFF_INBOUND_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr492460x2108R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49234Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_16_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49245Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_16IATU_UPPER_BASE_ADDR_OFF_INBOUND_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr492600x210CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_16_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49259Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_16IATU_LIMIT_ADDR_OFF_INBOUND_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr492870x2110R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49276Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_16_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49286Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_16IATU_LWR_TARGET_ADDR_OFF_INBOUND_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr493260x2114R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49312Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_16_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49325Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr493420x2118R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_16_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49341Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr493740x2120R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49361Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_16_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49373Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_17IATU_REGION_CTRL_1_OFF_INBOUND_17PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr494870x2300R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49388When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49401When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49414When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49427When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49440When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49452Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49466When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_17_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49486Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_17IATU_REGION_CTRL_2_OFF_INBOUND_17PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr497820x2304R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49512MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49537BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49555Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49566TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49577TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49589ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49602TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49616Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49635Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49648PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49664Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49680Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49699Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49714CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49726Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49771Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_17_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49781Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_17IATU_LWR_BASE_ADDR_OFF_INBOUND_17PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr498190x2308R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49807Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_17_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49818Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_17IATU_UPPER_BASE_ADDR_OFF_INBOUND_17PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr498330x230CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_17_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49832Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_17IATU_LIMIT_ADDR_OFF_INBOUND_17PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr498600x2310R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49849Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_17_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49859Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_17IATU_LWR_TARGET_ADDR_OFF_INBOUND_17PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr498990x2314R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49885Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_17_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49898Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr499150x2318R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_17_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49914Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr499470x2320R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49934Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_17_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49946Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_18IATU_REGION_CTRL_1_OFF_INBOUND_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr500600x2500R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49961When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49974When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr49987When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50000When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50013When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50025Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50039When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_18_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50059Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_18IATU_REGION_CTRL_2_OFF_INBOUND_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr503550x2504R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50085MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50110BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50128Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50139TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50150TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50162ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50175TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50189Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50208Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50221PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50237Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50253Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50272Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50287CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50299Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50344Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_18_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50354Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_18IATU_LWR_BASE_ADDR_OFF_INBOUND_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr503920x2508R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50380Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_18_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50391Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_18IATU_UPPER_BASE_ADDR_OFF_INBOUND_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr504060x250CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_18_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50405Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_18IATU_LIMIT_ADDR_OFF_INBOUND_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr504330x2510R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50422Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_18_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50432Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_18IATU_LWR_TARGET_ADDR_OFF_INBOUND_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr504720x2514R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50458Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_18_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50471Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr504880x2518R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_18_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50487Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr505200x2520R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50507Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_18_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50519Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_19IATU_REGION_CTRL_1_OFF_INBOUND_19PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr506330x2700R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50534When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50547When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50560When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50573When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50586When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50598Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50612When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_19_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50632Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_19IATU_REGION_CTRL_2_OFF_INBOUND_19PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr509280x2704R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50658MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50683BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50701Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50712TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50723TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50735ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50748TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50762Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50781Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50794PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50810Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50826Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50845Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50860CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50872Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50917Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_19_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50927Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_19IATU_LWR_BASE_ADDR_OFF_INBOUND_19PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr509650x2708R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50953Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_19_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50964Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_19IATU_UPPER_BASE_ADDR_OFF_INBOUND_19PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr509790x270CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_19_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50978Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_19IATU_LIMIT_ADDR_OFF_INBOUND_19PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr510060x2710R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr50995Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_19_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51005Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_19IATU_LWR_TARGET_ADDR_OFF_INBOUND_19PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr510450x2714R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51031Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_19_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51044Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr510610x2718R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_19_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51060Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr510930x2720R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51080Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_19_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51092Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_20IATU_REGION_CTRL_1_OFF_INBOUND_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr512060x2900R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51107When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51120When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51133When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51146When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51159When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51171Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51185When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_20_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51205Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_20IATU_REGION_CTRL_2_OFF_INBOUND_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr515010x2904R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51231MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51256BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51274Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51285TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51296TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51308ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51321TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51335Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51354Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51367PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51383Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51399Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51418Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51433CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51445Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51490Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_20_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51500Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_20IATU_LWR_BASE_ADDR_OFF_INBOUND_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr515380x2908R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51526Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_20_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51537Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_20IATU_UPPER_BASE_ADDR_OFF_INBOUND_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr515520x290CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_20_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51551Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_20IATU_LIMIT_ADDR_OFF_INBOUND_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr515790x2910R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51568Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_20_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51578Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_20IATU_LWR_TARGET_ADDR_OFF_INBOUND_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr516180x2914R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51604Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_20_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51617Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr516340x2918R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_20_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51633Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr516660x2920R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51653Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_20_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51665Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_21IATU_REGION_CTRL_1_OFF_INBOUND_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr517790x2B00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51680When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51693When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51706When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51719When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51732When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51744Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51758When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_21_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51778Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_21IATU_REGION_CTRL_2_OFF_INBOUND_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr520740x2B04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51804MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51829BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51847Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51858TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51869TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51881ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51894TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51908Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51927Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51940PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51956Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51972Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr51991Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52006CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52018Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52063Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_21_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52073Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_21IATU_LWR_BASE_ADDR_OFF_INBOUND_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr521110x2B08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52099Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_21_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52110Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_21IATU_UPPER_BASE_ADDR_OFF_INBOUND_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr521250x2B0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_21_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52124Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_21IATU_LIMIT_ADDR_OFF_INBOUND_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr521520x2B10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52141Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_21_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52151Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_21IATU_LWR_TARGET_ADDR_OFF_INBOUND_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr521910x2B14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52177Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_21_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52190Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr522070x2B18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_21_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52206Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr522390x2B20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52226Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_21_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52238Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_22IATU_REGION_CTRL_1_OFF_INBOUND_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr523520x2D00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52253When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52266When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52279When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52292When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52305When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52317Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52331When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_22_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52351Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_22IATU_REGION_CTRL_2_OFF_INBOUND_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr526470x2D04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52377MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52402BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52420Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52431TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52442TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52454ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52467TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52481Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52500Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52513PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52529Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52545Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52564Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52579CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52591Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52636Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_22_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52646Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_22IATU_LWR_BASE_ADDR_OFF_INBOUND_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr526840x2D08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52672Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_22_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52683Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_22IATU_UPPER_BASE_ADDR_OFF_INBOUND_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr526980x2D0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_22_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52697Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_22IATU_LIMIT_ADDR_OFF_INBOUND_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr527250x2D10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52714Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_22_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52724Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_22IATU_LWR_TARGET_ADDR_OFF_INBOUND_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr527640x2D14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52750Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_22_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52763Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr527800x2D18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_22_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52779Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr528120x2D20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52799Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_22_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52811Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_23IATU_REGION_CTRL_1_OFF_INBOUND_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr529250x2F00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52826When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52839When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52852When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52865When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52878When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52890Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52904When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_23_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52924Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_23IATU_REGION_CTRL_2_OFF_INBOUND_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr532200x2F04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52950MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52975BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr52993Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53004TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53015TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53027ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53040TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53054Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53073Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53086PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53102Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53118Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53137Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53152CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53164Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53209Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_23_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53219Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_23IATU_LWR_BASE_ADDR_OFF_INBOUND_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr532570x2F08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53245Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_23_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53256Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_23IATU_UPPER_BASE_ADDR_OFF_INBOUND_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr532710x2F0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_23_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53270Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_23IATU_LIMIT_ADDR_OFF_INBOUND_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr532980x2F10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53287Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_23_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53297Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_23IATU_LWR_TARGET_ADDR_OFF_INBOUND_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr533370x2F14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53323Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_23_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53336Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr533530x2F18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_23_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53352Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr533850x2F20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53372Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_23_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53384Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_24IATU_REGION_CTRL_1_OFF_INBOUND_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr534980x3100R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53399When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53412When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53425When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53438When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53451When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53463Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53477When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_24_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53497Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_24IATU_REGION_CTRL_2_OFF_INBOUND_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr537930x3104R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53523MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53548BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53566Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53577TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53588TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53600ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53613TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53627Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53646Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53659PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53675Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53691Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53710Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53725CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53737Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53782Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_24_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53792Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_24IATU_LWR_BASE_ADDR_OFF_INBOUND_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr538300x3108R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53818Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_24_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53829Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_24IATU_UPPER_BASE_ADDR_OFF_INBOUND_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr538440x310CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_24_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53843Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_24IATU_LIMIT_ADDR_OFF_INBOUND_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr538710x3110R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53860Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_24_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53870Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_24IATU_LWR_TARGET_ADDR_OFF_INBOUND_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr539100x3114R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53896Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_24_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53909Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr539260x3118R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_24_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53925Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr539580x3120R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53945Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_24_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53957Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_25IATU_REGION_CTRL_1_OFF_INBOUND_25PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr540710x3300R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53972When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53985When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr53998When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54011When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54024When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54036Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54050When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_25_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54070Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_25IATU_REGION_CTRL_2_OFF_INBOUND_25PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr543660x3304R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54096MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54121BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54139Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54150TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54161TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54173ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54186TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54200Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54219Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54232PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54248Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54264Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54283Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54298CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54310Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54355Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_25_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54365Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_25IATU_LWR_BASE_ADDR_OFF_INBOUND_25PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr544030x3308R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54391Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_25_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54402Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_25IATU_UPPER_BASE_ADDR_OFF_INBOUND_25PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr544170x330CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_25_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54416Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_25IATU_LIMIT_ADDR_OFF_INBOUND_25PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr544440x3310R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54433Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_25_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54443Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_25IATU_LWR_TARGET_ADDR_OFF_INBOUND_25PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr544830x3314R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54469Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_25_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54482Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr544990x3318R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_25_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54498Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr545310x3320R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54518Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_25_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54530Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_26IATU_REGION_CTRL_1_OFF_INBOUND_26PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr546440x3500R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54545When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54558When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54571When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54584When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54597When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54609Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54623When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_26_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54643Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_26IATU_REGION_CTRL_2_OFF_INBOUND_26PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr549390x3504R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54669MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54694BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54712Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54723TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54734TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54746ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54759TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54773Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54792Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54805PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54821Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54837Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54856Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54871CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54883Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54928Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_26_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54938Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_26IATU_LWR_BASE_ADDR_OFF_INBOUND_26PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr549760x3508R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54964Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_26_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54975Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_26IATU_UPPER_BASE_ADDR_OFF_INBOUND_26PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr549900x350CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_26_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr54989Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_26IATU_LIMIT_ADDR_OFF_INBOUND_26PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr550170x3510R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55006Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_26_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55016Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_26IATU_LWR_TARGET_ADDR_OFF_INBOUND_26PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr550560x3514R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55042Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_26_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55055Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr550720x3518R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_26_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55071Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr551040x3520R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55091Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_26_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55103Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_27IATU_REGION_CTRL_1_OFF_INBOUND_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr552170x3700R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55118When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55131When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55144When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55157When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55170When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55182Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55196When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_27_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55216Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_27IATU_REGION_CTRL_2_OFF_INBOUND_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr555120x3704R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55242MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55267BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55285Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55296TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55307TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55319ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55332TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55346Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55365Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55378PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55394Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55410Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55429Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55444CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55456Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55501Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_27_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55511Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_27IATU_LWR_BASE_ADDR_OFF_INBOUND_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr555490x3708R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55537Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_27_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55548Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_27IATU_UPPER_BASE_ADDR_OFF_INBOUND_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr555630x370CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_27_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55562Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_27IATU_LIMIT_ADDR_OFF_INBOUND_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr555900x3710R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55579Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_27_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55589Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_27IATU_LWR_TARGET_ADDR_OFF_INBOUND_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr556290x3714R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55615Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_27_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55628Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr556450x3718R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_27_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55644Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr556770x3720R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55664Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_27_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55676Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_28IATU_REGION_CTRL_1_OFF_INBOUND_28PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr557900x3900R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55691When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55704When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55717When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55730When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55743When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55755Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55769When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_28_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55789Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_28IATU_REGION_CTRL_2_OFF_INBOUND_28PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr560850x3904R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55815MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55840BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55858Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55869TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55880TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55892ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55905TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55919Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55938Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55951PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55967Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr55983Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56002Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56017CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56029Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56074Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_28_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56084Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_28IATU_LWR_BASE_ADDR_OFF_INBOUND_28PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr561220x3908R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56110Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_28_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56121Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_28IATU_UPPER_BASE_ADDR_OFF_INBOUND_28PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr561360x390CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_28_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56135Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_28IATU_LIMIT_ADDR_OFF_INBOUND_28PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr561630x3910R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56152Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_28_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56162Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_28IATU_LWR_TARGET_ADDR_OFF_INBOUND_28PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr562020x3914R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56188Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_28_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56201Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr562180x3918R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_28_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56217Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr562500x3920R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56237Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_28_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56249Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_29IATU_REGION_CTRL_1_OFF_INBOUND_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr563630x3B00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56264When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56277When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56290When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56303When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56316When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56328Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56342When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_29_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56362Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_29IATU_REGION_CTRL_2_OFF_INBOUND_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr566580x3B04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56388MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56413BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56431Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56442TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56453TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56465ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56478TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56492Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56511Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56524PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56540Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56556Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56575Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56590CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56602Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56647Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_29_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56657Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_29IATU_LWR_BASE_ADDR_OFF_INBOUND_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr566950x3B08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56683Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_29_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56694Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_29IATU_UPPER_BASE_ADDR_OFF_INBOUND_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr567090x3B0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_29_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56708Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_29IATU_LIMIT_ADDR_OFF_INBOUND_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr567360x3B10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56725Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_29_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56735Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_29IATU_LWR_TARGET_ADDR_OFF_INBOUND_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr567750x3B14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56761Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_29_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56774Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr567910x3B18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_29_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56790Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr568230x3B20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56810Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_29_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56822Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_30IATU_REGION_CTRL_1_OFF_INBOUND_30PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr569360x3D00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56837When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56850When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56863When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56876When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56889When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56901Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56915When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_30_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56935Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_30IATU_REGION_CTRL_2_OFF_INBOUND_30PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr572310x3D04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56961MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr56986BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57004Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57015TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57026TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57038ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57051TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57065Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57084Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57097PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57113Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57129Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57148Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57163CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57175Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57220Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_30_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57230Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_30IATU_LWR_BASE_ADDR_OFF_INBOUND_30PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr572680x3D08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57256Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_30_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57267Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_30IATU_UPPER_BASE_ADDR_OFF_INBOUND_30PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr572820x3D0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_30_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57281Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_30IATU_LIMIT_ADDR_OFF_INBOUND_30PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr573090x3D10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57298Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_30_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57308Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_30IATU_LWR_TARGET_ADDR_OFF_INBOUND_30PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr573480x3D14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57334Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_30_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57347Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr573640x3D18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_30_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57363Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr573960x3D20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57383Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_30_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57395Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_1_OFF_INBOUND_31IATU_REGION_CTRL_1_OFF_INBOUND_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr575090x3F00R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31iATU Region Control 1 Register.falsefalsefalsefalseTYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57410When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).Note: This register field is sticky.400x00R/WTCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57423When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.750x0R/WTDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57436When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.880x0R/WATTRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_ATTR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57449When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.1090x0R/W--11110x0rTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57462When the TH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "TH Match Enable" bit of the "iATU Control 2 Register" is set. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.12120x0R/WINCREASE_REGION_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_INCREASE_REGION_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57474Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).Note: This register field is sticky.13130x0R/W--17140x0rPHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57488When the PH field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "PH Match Enable" bit of the "iATU Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.19180x0R/WCTRL_1_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_1_OFF_INBOUND_31_CTRL_1_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57508Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set.Note: This register field is sticky.22200x0R/W--31230x0rregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_REGION_CTRL_2_OFF_INBOUND_31IATU_REGION_CTRL_2_OFF_INBOUND_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr578040x3F04R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31iATU Region Control 2 Register.falsefalsefalsefalseMSG_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57534MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Control 2 Register" is set.Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.700x00R/WBAR_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_BAR_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57559BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.Note: This register field is sticky.1080x0R/W--12110x0rMSG_TYPE_MATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_TYPE_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57577Message Type Match Mode.When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated.Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.Note: This register field is sticky.13130x0R/WTC_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TC_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57588TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.14140x0R/WTD_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TD_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57599TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.15150x0R/WATTR_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_ATTR_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57611ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.Note: This register field is sticky.16160x0R/WTH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_TH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57624TH Match Enable. Ensures that a successful TH TLP field comparison match (see TH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.17170x0R/W--18180x0rFUNC_NUM_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUNC_NUM_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57638Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.Note: This register field is sticky.19190x0R/W--20200x0rMSG_CODE_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MSG_CODE_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57657Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs (in MSG transactions) for address translation to proceed.ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1Note: This register field is sticky.21210x0R/WPH_MATCH_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_PH_MATCH_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57670PH Match Enable. Ensures that a successful PH TLP field comparison match (see PH field of the "iATU Control 1 Register") occurs for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.Note: This register field is sticky.22220x0R/WSINGLE_ADDR_LOC_TRANS_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_SINGLE_ADDR_LOC_TRANS_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57686Single Address Location Translate Enable.When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region.The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.Note: This register field is sticky.23230x0R/WRESPONSE_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_RESPONSE_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57702Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved.Note: This register field is sticky.25240x0R/W--26260x0rFUZZY_TYPE_MATCH_CODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_FUZZY_TYPE_MATCH_CODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57721Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP.Note: This register field is sticky.27270x0R/WCFG_SHIFT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_CFG_SHIFT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57736CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.Note: This register field is sticky.28280x0R/WINVERT_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_INVERT_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57748Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).Note: This register field is sticky.29290x0R/WMATCH_MODEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_MATCH_MODE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57793Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC.For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number.For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored.Note: This register field is sticky.30300x0R/WREGION_ENPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_REGION_CTRL_2_OFF_INBOUND_31_REGION_EN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57803Region Enable. This bit must be set to '1' for address translation to take place.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_BASE_ADDR_OFF_INBOUND_31IATU_LWR_BASE_ADDR_OFF_INBOUND_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr578410x3F08R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.falsefalsefalsefalseLWR_BASE_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57829Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0.A write to this location is ignored by the PCIe controller.n is log2(CX_ATU_MIN_REGION_SIZE)1100x000RLWR_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_BASE_ADDR_OFF_INBOUND_31_LWR_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57840Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_BASE_ADDR_OFF_INBOUND_31IATU_UPPER_BASE_ADDR_OFF_INBOUND_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr578550x3F0CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31iATU Upper Base Address Register.falsefalsefalsefalseUPPER_BASE_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_BASE_ADDR_OFF_INBOUND_31_UPPER_BASE_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57854Forms bits [63:32] of the start (and end) address of the address region to be translated.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LIMIT_ADDR_OFF_INBOUND_31IATU_LIMIT_ADDR_OFF_INBOUND_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr578820x3F10R/W0x00000fffPE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31iATU Limit Address Register.falsefalsefalsefalseLIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57871Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones.A write to this location is ignored by the PCIe controller.1100xfffRLIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LIMIT_ADDR_OFF_INBOUND_31_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57881Forms upper bits of the end address of the address region to be translated.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_LWR_TARGET_ADDR_OFF_INBOUND_31IATU_LWR_TARGET_ADDR_OFF_INBOUND_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr579210x3F14R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31iATU Lower Target Address Register.falsefalsefalsefalseLWR_TARGET_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57907Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.1100x000RLWR_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_LWR_TARGET_ADDR_OFF_INBOUND_31_LWR_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57920Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr579370x3F18R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31iATU Upper Target Address Register.falsefalsefalsefalseUPPER_TARGET_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_31_UPPER_TARGET_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57936Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_ATU_CAP.IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr579690x3F20R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31iATU Upper Limit Address Register. The CX_MAX_ATU_REGION_SIZE configuration parameter (Value Range: 0->32, 8=1TB) specifies the maximum region size of an address translation region. This register is only used when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.falsefalsefalsefalseUPPR_LIMIT_ADDR_RWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_RW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57956Forms the LSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'Note: This register field is sticky.700x00R/WUPPR_LIMIT_ADDR_HWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_ATU_CAP_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_31_UPPR_LIMIT_ADDR_HW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr57968Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'.3180x000000RgroupPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAPPF0_DMA_CAPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr643180x80000R/WPE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAPDMA Port Logic StructureregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CTRL_DATA_ARB_PRIOR_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CTRL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_EN_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_DOORBELL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_EN_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_DOORBELL_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_MASK_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_CLEAR_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ERR_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_LOW_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_HIGH_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_LOW_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_HIGH_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH01_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH23_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH45_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH67_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_LINKED_LIST_ERR_EN_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_INT_STATUS_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_INT_MASK_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_INT_CLEAR_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_LOW_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_HIGH_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_LINKED_LIST_ERR_EN_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_LOW_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_HIGH_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_LOW_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_HIGH_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CH01_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CH23_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CH45_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CH67_IMWR_DATA_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFFregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_0registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_1registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_2registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_3registerPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CTRL_DATA_ARB_PRIOR_OFFDMA_CTRL_DATA_ARB_PRIOR_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr580480x0R/W0x00000688PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFFDMA Arbitration Scheme for TRGT1 Interface. This register is used to control traffic priorities among various sources that are delivered to your application through TRGT1 where 0x0 represents the highest priority. - Non-DMA Rx Requests - DMA Write Channel MRd Requests (DMA data requests and LL element/descriptor access) - DMA Read Channel MRd Requests (LL element/descriptor access) - DMA Read Channel MWr RequestsConcurrent traffic from channels with same priority are sorted according to Round-Robin arbitration rules.The arbitration priority defaults to Non-DMA requests (highest), Write Channel MRd, Read Channel MRd, Read Channel MWr.For more details, see the For more details, see the Internal Architecture section in the DMA chapter of the Databook.falsefalsefalsefalseRTRGT1_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58004Non-DMA Rx Requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 200x0R/WWR_CTRL_TRGT_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58016DMA Write Channel MRd Requests. For DMA data requests and LL element/descriptor access.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 530x1R/WRD_CTRL_TRGT_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58028DMA Read Channel MRd Requests. For LL element/descriptor access.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 860x2R/WRDBUFF_TRGT_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58039DMA Read Channel MWr Requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1190x3R/WRSVDP_12PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58047Reserved for future use.31120x00000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CTRL_OFFDMA_CTRL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr581240x8R/W0x00040004PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CTRL_OFFDMA Number of Channels Register.falsefalsefalsefalseNUM_DMA_WR_CHANPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58061Number of Write Channels. You can read this register to determine the number of write channels the DMA controller has been configured to support.300x4RRSVDP_4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_4_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58069Reserved for future use.1540x000RNUM_DMA_RD_CHANPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58079Number of Read Channels. You can read this register to determine the number of read channels the DMA controller has been configured to support.19160x4RRSVDP_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_20_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58087Reserved for future use.23200x0RDIS_C2W_CACHE_WRPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58101Disable DMA Write Channels "completion to memory write" context cache pre-fetch function.Note: For internal debugging only.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24240x0R/WDIS_C2W_CACHE_RDPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58115Disable DMA Read Channels "completion to memory write" context cache pre-fetch function.Note: For internal debugging only.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 25250x0R/WRSVDP_26PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CTRL_OFF_RSVDP_26_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58123Reserved for future use.31260x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_EN_OFFDMA_WRITE_ENGINE_EN_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr582830xCR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFFDMA Write Engine Enable Register.falsefalsefalsefalseDMA_WRITE_ENGINEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58178DMA Write Engine Enable. - 1: Enable - 0: Disable (Soft Reset)For normal operation, you must initially set this bit to "1", before any other software setup actions. You do not need to toggle or rewrite to this bit during normal operation.You should set this bit to "0" when you want to "Soft Reset" the DMA controller write logic. There are three possible reasons for resetting the DMA controller write logic: - The "Abort Interrupt Status" bit is set (in the "DMA Write Interrupt Status Register" DMA_WRITE_INT_STATUS_OFF), and any of the bits is in the "DMA Write Error Status Register" (DMA_WRITE_ERR_STATUS_OFF) are set. Resetting the DMA controller write logic re-initializes the control logic, ensuring that the next DMA write transfer is executed successfully. - You have executed the procedure outlined in "Stop Bit" , after which, the "Abort Interrupt Status" bit is set and the Channel Status field (CS) of the DMA write "DMA Channel Control 1 Register " (DMA_CH_CONTROL1_OFF_WRCH_0) is set to "Stopped." Resetting the DMA controller write logic re-initializes the control logic ensuring that the next DMA write transfer is executed successfully. - During software development, when you incorrectly program the DMA write engine.To "Soft Reset" the DMA controller write logic, you must: - De-assert the DMA write engine enable bit. - Wait for the DMA to complete any in-progress TLP transfer, by waiting until a read on the DMA write engine enable bit returns a "0". - Assert the DMA write engine enable bit.This "Soft Reset" does not clear the DMA configuration registers. The DMA write transfer does not start until you write to the "DMA Write Doorbell Register" (DMA_WRITE_DOORBELL_OFF).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58186Reserved for future use.1510x0000RDMA_WRITE_ENGINE_EN_HSHAKE_CH0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58197Enable Handshake for DMA Write Engine Channel 0.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 16160x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58208Enable Handshake for DMA Write Engine Channel 1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 17170x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58219Enable Handshake for DMA Write Engine Channel 2.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 18180x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58230Enable Handshake for DMA Write Engine Channel 3.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 19190x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH4_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58241Enable Handshake for DMA Write Engine Channel 4.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 20200x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH5_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58252Enable Handshake for DMA Write Engine Channel 5.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 21210x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH6_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58263Enable Handshake for DMA Write Engine Channel 6.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 22220x0R/WDMA_WRITE_ENGINE_EN_HSHAKE_CH7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH7_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58274Enable Handshake for DMA Write Engine Channel 7.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23230x0R/WRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58282Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_DOORBELL_OFFDMA_WRITE_DOORBELL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr583360x10R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFFDMA Write Doorbell Register.falsefalsefalsefalseWR_DOORBELL_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58306Doorbell Number. You must write the channel number to this register to start the DMA write transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. You do not need to toggle or write any other value to this register to start a new transfer.The range of this field is 0x0 to 0x7, and 0x0 corresponds to channel 0. Also note that a write to this field triggers the controller to exit L1 substates.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 200x0R/WRSVDP_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_RSVDP_3_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58314Reserved for future use.3030x0000000RWR_STOPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DOORBELL_OFF_WR_STOP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58335Stop. Set in conjunction with the Doorbell Number field. The DMA write channel stops issuing requests, sets the channel status to "Stopped", and asserts the "Abort" interrupt if it is enabled. Before setting the Stop bit, you must read the channel Status field (CS) of the "DMA Channel Control 1 Register " (DMA_CH_CONTROL1_OFF_WRCH_0) to ensure that the write channel is "Running" (transferring data).For more information, see "Stopping the DMA Transfer (Software Stop)."Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFFDMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr584180x18R/W0x00008421PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFFDMA Write Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for write channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to the arbitration routine. When the channel weight count is reached or DMA channel request transfer size reaches zero, the WWR arbiter selects the next channel to be processed. Your software must initialize this register before ringing the doorbell. For more details, see "Multichannel Arbitration". Value range is (0-0x1F) corresponding to (1-32) transaction requests.falsefalsefalsefalseWRITE_CHANNEL0_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58364Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 400x01R/WWRITE_CHANNEL1_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58379Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 950x01R/WWRITE_CHANNEL2_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58394Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 14100x01R/WWRITE_CHANNEL3_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58409Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 19150x01R/WRSVDP_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58417Reserved for future use.31200x000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFFDMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr585000x1CR/W0x00008421PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFFDMA Write Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for write channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to the arbitration routine. When the channel weight count is reached or DMA channel request transfer size reaches zero, the WWR arbiter selects the next channel to be processed. Your software must initialize this register before ringing the doorbell. For more details, see "Multichannel Arbitration". Value range is (0-0x1F) corresponding to (1-32) transaction requests.falsefalsefalsefalseWRITE_CHANNEL4_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58446Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 400x01R/WWRITE_CHANNEL5_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58461Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 950x01R/WWRITE_CHANNEL6_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58476Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 14100x01R/WWRITE_CHANNEL7_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58491Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued before moving to the next channel.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 19150x01R/WRSVDP_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58499Reserved for future use.31200x000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_EN_OFFDMA_READ_ENGINE_EN_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr586580x2CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFFDMA Read Engine Enable Register.falsefalsefalsefalseDMA_READ_ENGINEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58553DMA Read Engine Enable. - 1: Enable - 0: Disable (Soft Reset)For normal operation, you must initially set this bit to "1", before any other software setup actions. You do not need to toggle or rewrite to this bit during normal operation.You should set this field to "0" when you want to "Soft Reset" the DMA controller read logic. There are three possible reasons for resetting the DMA controller read logic: - The "Abort Interrupt Status" bit is set (in the "DMA Read Interrupt Status Register" (DMA_READ_INT_STATUS_OFF), and any of the bits in the "DMA Read Error Status Low Register" (DMA_READ_ERR_STATUS_LOW_OFF) is set. Resetting the DMA controller read logic re-initializes the control logic, ensuring that the next DMA read transfer is executed successfully. - You have executed the procedure outlined in "Stop Bit", after which, the "Abort Interrupt Status" bit is set and the channel Status field (CS) of the DMA read "DMA Channel Control 1 Register " (DMA_CH_CONTROL1_OFF_WRCH_0) is set to "Stopped". Resetting the DMA controller read logic re-initializes the control logic ensuring that the next DMA read transfer is executed successfully. - During software development, when you incorrectly program the DMA read engine.To "Soft Reset" the DMA controller read logic, you must: - De-assert the DMA read engine enable bit. - Wait for the DMA to complete any in-progress TLP transfer, by waiting until a read on the DMA read engine enable bit returns a "0". - Assert the DMA read engine enable bit.This "Soft Reset" does not clear the DMA configuration registers. The DMA read transfer does not start until you write to the "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_1_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58561Reserved for future use.1510x0000RDMA_READ_ENGINE_EN_HSHAKE_CH0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58572Enable Handshake for DMA Read Engine Channel 0.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 16160x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58583Enable Handshake for DMA Read Engine Channel 1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 17170x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58594Enable Handshake for DMA Read Engine Channel 2.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 18180x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58605Enable Handshake for DMA Read Engine Channel 3.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 19190x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH4_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58616Enable Handshake for DMA Read Engine Channel 4.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 20200x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH5_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58627Enable Handshake for DMA Read Engine Channel 5.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 21210x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH6_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58638Enable Handshake for DMA Read Engine Channel 6.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 22220x0R/WDMA_READ_ENGINE_EN_HSHAKE_CH7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH7_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58649Enable Handshake for DMA Read Engine Channel 7.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23230x0R/WRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_EN_OFF_RSVDP_24_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58657Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_DOORBELL_OFFDMA_READ_DOORBELL_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr587090x30R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_DOORBELL_OFFDMA Read Doorbell Register.falsefalsefalsefalseRD_DOORBELL_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58679Doorbell Number. You must write 0x0 to this register to start the DMA read transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change.The range of this field is 0x0 to 0x7, and 0x0 corresponds to channel 0. Also note that a write to this field triggers the controller to exit L1 substates.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 200x0R/WRSVDP_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RSVDP_3_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58687Reserved for future use.3030x0000000RRD_STOPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DOORBELL_OFF_RD_STOP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58708Stop. Set in conjunction with the Doorbell Number field. The DMA read channel stops issuing requests, sets the channel status to "Stopped", and asserts the "Abort" interrupt if it is enabled. Before setting the Stop bit, you must read the channel Status field (CS) of the "DMA Channel Control 1 Register " (DMA_CH_CONTROL1_OFF_RDCH_0) to ensure that the read channel is "Running" (transferring data).For more information, see "Stopping the DMA Transfer (Software Stop)".Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFFDMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr587860x38R/W0x00008421PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFFDMA Read Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for read channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to the arbitration routine. When the channel weight count is reached or DMA channel request transfer size reaches zero, the WWR arbiter selects the next channel to be processed. Your software must initialize this register before ringing the doorbell. For more details, see "Multichannel Arbitration". Value range is (0-0x1F) corresponding to (1-32) transaction requests.falsefalsefalsefalseREAD_CHANNEL0_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58735Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 400x01R/WREAD_CHANNEL1_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58749Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 950x01R/WREAD_CHANNEL2_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58763Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 14100x01R/WREAD_CHANNEL3_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58777Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 19150x01R/WRSVDP_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58785Reserved for future use.31200x000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFFDMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr588630x3CR/W0x00008421PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFFDMA Read Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for read channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to the arbitration routine. When the channel weight count is reached or DMA channel request transfer size reaches zero, the WWR arbiter selects the next channel to be processed. Your software must initialize this register before ringing the doorbell. For more details, see "Multichannel Arbitration". Value range is (0-0x1F) corresponding to (1-32) transaction requests.falsefalsefalsefalseREAD_CHANNEL4_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58812Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 400x01R/WREAD_CHANNEL5_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58826Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 950x01R/WREAD_CHANNEL6_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58840Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 14100x01R/WREAD_CHANNEL7_WEIGHTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58854Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 19150x01R/WRSVDP_20PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58862Reserved for future use.31200x000RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_STATUS_OFFDMA_WRITE_INT_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr589370x4CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFFDMA Write Interrupt Status Register.falsefalsefalsefalseWR_DONE_INT_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58893Done Interrupt Status. The DMA write channel has successfully completed the DMA transfer. For more details, see "Interrupts and Error Handling". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA write interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the DMA write interrupt Clear register to clear this interrupt bit. Note: You can write to this register to emulate interrupt generation, during software or hardware testing. A write to the address triggers an interrupt, but the DMA does not set the Done or Abort bits in this register.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 700x00R/WRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58901Reserved for future use.1580x00RWR_ABORT_INT_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58928Abort Interrupt Status. The DMA write channel has detected an error, or you manually stopped the transfer as described in "Error Handling Assistance by Remote Software". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA write interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the DMA write interrupt Clear register to clear this interrupt bit. Note: You can write to this register to emulate interrupt generation, during software or hardware testing. A write to the address triggers an interrupt, but the DMA does not set the Done or Abort bits in this register.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23160x00R/WRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58936Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_MASK_OFFDMA_WRITE_INT_MASK_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr589850x54R/W0x000f000fPE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFFDMA Write Interrupt Mask Register.falsefalsefalsefalseWR_DONE_INT_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58954Done Interrupt Mask. Prevents the Done interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 300xfR/W--740x0rRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_8_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58962Reserved for future use.1580x00RWR_ABORT_INT_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58976Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 19160xfR/W--23200x0rRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_MASK_OFF_RSVDP_24_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr58984Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_INT_CLEAR_OFFDMA_WRITE_INT_CLEAR_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr590370x58R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFFDMA Write Interrupt Clear Register.falsefalsefalsefalseWR_DONE_INT_CLEARPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59004Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: Reading from this self-clearing register field always returns a "0".300x0W--740x0rRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59012Reserved for future use.1580x00RWR_ABORT_INT_CLEARPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59028Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: Reading from this self-clearing register field always returns a "0".19160x0W--23200x0rRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59036Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ERR_STATUS_OFFDMA_WRITE_ERR_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr590990x5CR0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFFDMA Write Error Status RegisterfalsefalsefalsefalseAPP_READ_ERR_DETECTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59062Application Read Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading data from it. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA write interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Write Interrupt Clear Register" (DMA_WRITE_INT_CLEAR_OFF) to clear this error bit.700x00RRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59069Reserved for future use.1580x00RLINKLIST_ELEMENT_FETCH_ERR_DETECTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59091Linked List Element Fetch Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading a linked list element from local memory. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA write interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Write Interrupt Clear Register" (DMA_WRITE_INT_CLEAR_OFF) to clear this error bit.23160x00RRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59098Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_LOW_OFFDMA_WRITE_DONE_IMWR_LOW_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr591160x60R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFFDMA Write Done IMWr Address Low Register.falsefalsefalsefalseDMA_WRITE_DONE_LOW_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59115The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be "00" as this address must be dword aligned.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_DONE_IMWR_HIGH_OFFDMA_WRITE_DONE_IMWR_HIGH_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr591320x64R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFFDMA Write Done IMWr Interrupt Address High Register.falsefalsefalsefalseDMA_WRITE_DONE_HIGH_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59131The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_LOW_OFFDMA_WRITE_ABORT_IMWR_LOW_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr591500x68R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFFDMA Write Abort IMWr Address Low Register.falsefalsefalsefalseDMA_WRITE_ABORT_LOW_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59149The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP it generates. Bits [1:0] must be "00" as this address must be dword aligned.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ABORT_IMWR_HIGH_OFFDMA_WRITE_ABORT_IMWR_HIGH_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr591660x6CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFFDMA Write Abort IMWr Address High Register.falsefalsefalsefalseDMA_WRITE_ABORT_HIGH_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59165The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH01_IMWR_DATA_OFFDMA_WRITE_CH01_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr591940x70R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFFDMA Write Channel 1 and 0 IMWr Data Register.falsefalsefalsefalseWR_CHANNEL_0_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59181The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 0.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1500x0000R/WWR_CHANNEL_1_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59193The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH23_IMWR_DATA_OFFDMA_WRITE_CH23_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr592220x74R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFFDMA Write Channel 3 and 2 IMWr Data Register.falsefalsefalsefalseWR_CHANNEL_2_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59209The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 2.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1500x0000R/WWR_CHANNEL_3_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59221The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 3.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH45_IMWR_DATA_OFFDMA_WRITE_CH45_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr592500x78R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFFDMA Write Channel 5 and 4 IMWr Data Register.falsefalsefalsefalseWR_CHANNEL_4_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59237The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 4.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1500x0000R/WWR_CHANNEL_5_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59249The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 5.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_CH67_IMWR_DATA_OFFDMA_WRITE_CH67_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr592780x7CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFFDMA Write Channel 7 and 6 IMWr Data Register.falsefalsefalsefalseWR_CHANNEL_6_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59265The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 6.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1500x0000R/WWR_CHANNEL_7_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59277The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 7.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_LINKED_LIST_ERR_EN_OFFDMA_WRITE_LINKED_LIST_ERR_EN_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr593360x90R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFFDMA Write Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel "done" interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel "abort" interrupts (local and remote).falsefalsefalsefalseWR_CHANNEL_LLRAIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59302Write Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the write channel remote abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Used in linked list mode only.For more details, see "Interrupt Handling".Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 300x0R/W--740x0rRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59310Reserved for future use.1580x00RWR_CHANNEL_LLLAIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59327Write Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the write channel local abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Used in linked list mode only.For more details, see "Interrupt Handling".Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 19160x0R/W--23200x0rRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59335Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_INT_STATUS_OFFDMA_READ_INT_STATUS_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr594130xA0R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFFDMA Read Interrupt Status Register.falsefalsefalsefalseRD_DONE_INT_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59365Done Interrupt Status. The DMA read channel has successfully completed the DMA read transfer.Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the DMA read interrupt Clear register to clear this interrupt bit. Note: You can write to this register to emulate interrupt generation, during software or hardware testing. A write to the address triggers an interrupt, but the DMA does not set the Done or Abort bits in this register.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 700x00R/WRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_8_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59373Reserved for future use.1580x00RRD_ABORT_INT_STATUSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59404Abort Interrupt Status. The DMA read channel has detected an error, or you manually stopped the transfer as described in "Stopping the DMA Transfer (Software Stop)". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.You can read the "DMA Read Error Status Low Register" (DMA_READ_ERR_STATUS_LOW_OFF) and "DMA Read Error Status High Register" (DMA_READ_ERR_STATUS_HIGH_OFF) to determine the source of the error. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the DMA read interrupt Clear register to clear this interrupt bit. Note: You can write to this register to emulate interrupt generation, during software or hardware testing. A write to the address triggers an interrupt, but the DMA does not set the Done or Abort bits in this register.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23160x00R/WRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_STATUS_OFF_RSVDP_24_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59412Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_INT_MASK_OFFDMA_READ_INT_MASK_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr594610xA8R/W0x000f000fPE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_INT_MASK_OFFDMA Read Interrupt Mask Register.falsefalsefalsefalseRD_DONE_INT_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59430Done Interrupt Mask. Prevents the Done interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 300xfR/W--740x0rRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_8_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59438Reserved for future use.1580x00RRD_ABORT_INT_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59452Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 19160xfR/W--23200x0rRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_MASK_OFF_RSVDP_24_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59460Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_INT_CLEAR_OFFDMA_READ_INT_CLEAR_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr595130xACR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFFDMA Read Interrupt Clear Register.falsefalsefalsefalseRD_DONE_INT_CLEARPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59480Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: Reading from this self-clearing register field always returns a "0".700x00WRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_8_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59488Reserved for future use.1580x00RRD_ABORT_INT_CLEARPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59504Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Note: Reading from this self-clearing register field always returns a "0".23160x00WRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_INT_CLEAR_OFF_RSVDP_24_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59512Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_LOW_OFFDMA_READ_ERR_STATUS_LOW_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr595810xB4R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFFDMA Read Error Status Low Register.falsefalsefalsefalseAPP_WR_ERR_DETECTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59543Application Write Error Detected. The DMA read channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while writing data to it. This error is fatal. You must restart the transfer from the beginning, as the channel context is corrupted, and the transfer is not rolled back. For more details, see "Linked List Mode". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this clears all bits in this register, and also the DMA Read Error Status High register (DMA_READ_ERR_STATUS_HIGH_OFF).700x00RRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59550Reserved for future use.1580x00RLINK_LIST_ELEMENT_FETCH_ERR_DETECTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59573Linked List Element Fetch Error Detected. - The DMA read channel has received an error response from the AXI bus while reading a linked list element from local memory. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this clears all bits in this register, and also the DMA Read Error Status High register (DMA_READ_ERR_STATUS_HIGH_OFF).23160x00RRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59580Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ERR_STATUS_HIGH_OFFDMA_READ_ERR_STATUS_HIGH_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr596820xB8R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFFDMA Read Error Status High Register.falsefalsefalsefalseUNSUPPORTED_REQPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59608Unsupported Request. The DMA read channel has received a PCIe unsupported request completion status from the remote device in response to the MRd request. For more details, see "Linked List Mode". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this also clears the other error bits for the same channel in this register and in the DMA Read Error Status Low register.700x00RCPL_ABORTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59632Completer Abort. The DMA read channel has received a PCIe completer abort completion status from the remote device in response to the MRd request. For more details, see "Linked List Mode".Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this also clears the other error bits for the same channel in this register and in the DMA Read Error Status Low register.1580x00RCPL_TIMEOUTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59655Completion Time Out. The DMA read channel has timed-out while waiting for the remote device to respond to the MRd request, or a malformed CplD has been received. For more details, see "Linked List Mode". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling" . - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this also clears the other error bits for the same channel in this register and in the DMA Read Error Status Low register.23160x00RDATA_POISIONINGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59681Data Poisoning. The DMA read channel has detected data poisoning in the completion from the remote device (in response to the MRd request).The DMA read channel will drop the completion and then be halted. The CX_FLT_MASK_UR_POIS filter rule does not affect this behavior.Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this also clears the other error bits for the same channel in this register and in the DMA Read Error Status Low register.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_LINKED_LIST_ERR_EN_OFFDMA_READ_LINKED_LIST_ERR_EN_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr597390xC4R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFFDMA Read Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel "done" interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel "abort" interrupts (local and remote).falsefalsefalsefalseRD_CHANNEL_LLRAIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59705Read Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the read channel Remote Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Used in linked list mode only.For more details, see "Interrupt Handling".Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 300x0R/W--740x0rRSVDP_8PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59713Reserved for future use.1580x00RRD_CHANNEL_LLLAIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59730Read Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the read channel Local Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.Used in linked list mode only.For more details, see "Interrupt Handling".Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 19160x0R/W--23200x0rRSVDP_24PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59738Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_LOW_OFFDMA_READ_DONE_IMWR_LOW_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr597560xCCR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFFDMA Read Done IMWr Address Low Register.falsefalsefalsefalseDMA_READ_DONE_LOW_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59755The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be "00" as this address must be dword aligned.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_DONE_IMWR_HIGH_OFFDMA_READ_DONE_IMWR_HIGH_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr597720xD0R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFFDMA Read Done IMWr Address High Register.falsefalsefalsefalseDMA_READ_DONE_HIGH_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59771The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_LOW_OFFDMA_READ_ABORT_IMWR_LOW_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr597890xD4R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFFDMA Read Abort IMWr Address Low Register.falsefalsefalsefalseDMA_READ_ABORT_LOW_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59788The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP. Bits [1:0] must be "00" as this address must be dword aligned.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ABORT_IMWR_HIGH_OFFDMA_READ_ABORT_IMWR_HIGH_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr598050xD8R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFFDMA Read Abort IMWr Address High Register.falsefalsefalsefalseDMA_READ_ABORT_HIGH_REGPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59804The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CH01_IMWR_DATA_OFFDMA_READ_CH01_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr598330xDCR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFFDMA Read Channel 1 and 0 IMWr Data Register.falsefalsefalsefalseRD_CHANNEL_0_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59820The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 0.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1500x0000R/WRD_CHANNEL_1_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59832The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CH23_IMWR_DATA_OFFDMA_READ_CH23_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr598610xE0R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFFDMA Read Channel 3 and 2 IMWr Data Register.falsefalsefalsefalseRD_CHANNEL_2_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59848The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 2.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1500x0000R/WRD_CHANNEL_3_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59860The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 3.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CH45_IMWR_DATA_OFFDMA_READ_CH45_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr598890xE4R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFFDMA Read Channel 5 and 4 IMWr Data Register.falsefalsefalsefalseRD_CHANNEL_4_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59876The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 4.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1500x0000R/WRD_CHANNEL_5_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59888The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 5.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_CH67_IMWR_DATA_OFFDMA_READ_CH67_IMWR_DATA_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr599170xE8R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFFDMA Read Channel 7 and 6 IMWr Data Register.falsefalsefalsefalseRD_CHANNEL_6_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59904The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 6.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1500x0000R/WRD_CHANNEL_7_DATAPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59916The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 7.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31160x0000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFFDMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr599900x108R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFFDMA Write Engine Handshake Counter Channel 0/1/2/3 Register.falsefalsefalsefalseDMA_WRITE_ENGINE_HSHAKE_CNT_CH0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59931DMA handshake counter for DMA Write Engine Channel 0. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.400x00RRSVDP_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59938Reserved for future use.750x0RDMA_WRITE_ENGINE_HSHAKE_CNT_CH1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59948DMA handshake counter for DMA Write Engine Channel 1. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.1280x00RRSVDP_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59955Reserved for future use.15130x0RDMA_WRITE_ENGINE_HSHAKE_CNT_CH2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59965DMA handshake counter for DMA Write Engine Channel 2. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.20160x00RRSVDP_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59972Reserved for future use.23210x0RDMA_WRITE_ENGINE_HSHAKE_CNT_CH3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59982DMA handshake counter for DMA Write Engine Channel 3. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.28240x00RRSVDP_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr59989Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFFDMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr600630x10CR0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFFDMA Write Engine Handshake Counter Channel 4/5/6/7 Register.falsefalsefalsefalseDMA_WRITE_ENGINE_HSHAKE_CNT_CH4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH4_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60004DMA handshake counter for DMA Write Engine Channel 4. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.400x00RRSVDP_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60011Reserved for future use.750x0RDMA_WRITE_ENGINE_HSHAKE_CNT_CH5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH5_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60021DMA handshake counter for DMA Write Engine Channel 5. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.1280x00RRSVDP_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60028Reserved for future use.15130x0RDMA_WRITE_ENGINE_HSHAKE_CNT_CH6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH6_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60038DMA handshake counter for DMA Write Engine Channel 6. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.20160x00RRSVDP_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60045Reserved for future use.23210x0RDMA_WRITE_ENGINE_HSHAKE_CNT_CH7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH7_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60055DMA handshake counter for DMA Write Engine Channel 7. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.28240x00RRSVDP_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60062Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFFDMA_READ_ENGINE_HSHAKE_CNT_LOW_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr601360x118R0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFFDMA Read Engine Handshake Counter Channel 0/1/2/3 Register.falsefalsefalsefalseDMA_READ_ENGINE_HSHAKE_CNT_CH0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60077DMA handshake counter for DMA Read Engine Channel 0. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.400x00RRSVDP_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_5_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60084Reserved for future use.750x0RDMA_READ_ENGINE_HSHAKE_CNT_CH1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60094DMA handshake counter for DMA Read Engine Channel 1. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.1280x00RRSVDP_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_13_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60101Reserved for future use.15130x0RDMA_READ_ENGINE_HSHAKE_CNT_CH2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60111DMA handshake counter for DMA Read Engine Channel 2. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.20160x00RRSVDP_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_21_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60118Reserved for future use.23210x0RDMA_READ_ENGINE_HSHAKE_CNT_CH3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60128DMA handshake counter for DMA Read Engine Channel 3. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.28240x00RRSVDP_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_RSVDP_29_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60135Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFFDMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFFPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr602090x11CR0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFFDMA Read Engine Handshake Counter Channel 4/5/6/7 Register.falsefalsefalsefalseDMA_READ_ENGINE_HSHAKE_CNT_CH4PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH4_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60150DMA handshake counter for DMA Read Engine Channel 4. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.400x00RRSVDP_5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_5_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60157Reserved for future use.750x0RDMA_READ_ENGINE_HSHAKE_CNT_CH5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH5_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60167DMA handshake counter for DMA Read Engine Channel 5. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.1280x00RRSVDP_13PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_13_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60174Reserved for future use.15130x0RDMA_READ_ENGINE_HSHAKE_CNT_CH6PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH6_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60184DMA handshake counter for DMA Read Engine Channel 6. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.20160x00RRSVDP_21PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_21_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60191Reserved for future use.23210x0RDMA_READ_ENGINE_HSHAKE_CNT_CH7PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH7_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60201DMA handshake counter for DMA Read Engine Channel 7. If CC_DMA_HSHAKE =1, the data transfer in Linked List mode starts only when the counter isnon-zero.28240x00RRSVDP_29PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF_RSVDP_29_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60208Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_0DMA_CH_CONTROL1_OFF_WRCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr605160x200R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0DMA Write Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CB_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60229Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60248Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60265Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60286Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60307Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60328Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Write Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60340Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60358Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60371Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60383Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60399Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Write Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_WRCH_0).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60411Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60433Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60447Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60461Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60475Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60487Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60501Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60515Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_0DMA_CH_CONTROL2_OFF_WRCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr605720x204R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0DMA Write Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_ST_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60532Steering Tag (ST). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_RESERVED3_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60544Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60557Processing Hints (PH). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_0_DMA_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60571TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_0DMA_TRANSFER_SIZE_OFF_WRCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr606030x208R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0DMA Write Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60602DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_0DMA_SAR_LOW_OFF_WRCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr606240x20CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0DMA Write SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60623Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Write: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_0DMA_SAR_HIGH_OFF_WRCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr606420x210R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0DMA Write SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60641Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_0DMA_DAR_LOW_OFF_WRCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr606630x214R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0DMA Write DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60662Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Write: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_0DMA_DAR_HIGH_OFF_WRCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr606820x218R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0DMA Write DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60681Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_0DMA_LLP_LOW_OFF_WRCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr607040x21CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0DMA Write Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60703Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_0DMA_LLP_HIGH_OFF_WRCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr607230x220R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0DMA Write Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60722Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_0DMA_CH_CONTROL1_OFF_RDCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr610300x300R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0DMA Read Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CB_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60743Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60762Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60779Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60800Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60821Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60842Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Read Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60854Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60872Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60885Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60897Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60913Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Read Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_RDCH_0).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60925Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60947Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60961Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60975Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr60989Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61001Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61015Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61029Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_0DMA_CH_CONTROL2_OFF_RDCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr610860x304R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0DMA Read Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_ST_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61046Steering Tag (ST). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_RESERVED3_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61058Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61071Processing Hints (PH). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_0_DMA_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61085TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_0DMA_TRANSFER_SIZE_OFF_RDCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr611170x308R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0DMA Read Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61116DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_0DMA_SAR_LOW_OFF_RDCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr611380x30CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0DMA Read SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61137Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Read: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_0DMA_SAR_HIGH_OFF_RDCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr611560x310R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0DMA Read SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61155Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_0DMA_DAR_LOW_OFF_RDCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr611770x314R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0DMA Read DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61176Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Read: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_0DMA_DAR_HIGH_OFF_RDCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr611950x318R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0DMA Read DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61194Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_0DMA_LLP_LOW_OFF_RDCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr612170x31CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0DMA Read Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61216Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_0DMA_LLP_HIGH_OFF_RDCH_0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr612360x320R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0DMA Read Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61235Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_1DMA_CH_CONTROL1_OFF_WRCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr615430x400R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1DMA Write Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CB_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61256Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61275Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61292Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61313Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61334Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61355Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Write Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61367Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61385Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61398Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61410Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61426Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Write Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_WRCH_0).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED2_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61438Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61460Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61474Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61488Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61502Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61514Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61528Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61542Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_1DMA_CH_CONTROL2_OFF_WRCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr615990x404R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1DMA Write Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_ST_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61559Steering Tag (ST). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_RESERVED3_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61571Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61584Processing Hints (PH). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_1_DMA_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61598TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_1DMA_TRANSFER_SIZE_OFF_WRCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr616300x408R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1DMA Write Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61629DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_1DMA_SAR_LOW_OFF_WRCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr616510x40CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1DMA Write SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61650Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Write: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_1DMA_SAR_HIGH_OFF_WRCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr616690x410R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1DMA Write SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61668Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_1DMA_DAR_LOW_OFF_WRCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr616900x414R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1DMA Write DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61689Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Write: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_1DMA_DAR_HIGH_OFF_WRCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr617090x418R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1DMA Write DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61708Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_1DMA_LLP_LOW_OFF_WRCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr617310x41CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1DMA Write Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61730Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_1DMA_LLP_HIGH_OFF_WRCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr617500x420R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1DMA Write Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61749Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_1DMA_CH_CONTROL1_OFF_RDCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr620570x500R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1DMA Read Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CB_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61770Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61789Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61806Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61827Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61848Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61869Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Read Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61881Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61899Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61912Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61924Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61940Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Read Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_RDCH_0).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED2_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61952Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61974Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr61988Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62002Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62016Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62028Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62042Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62056Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_1DMA_CH_CONTROL2_OFF_RDCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr621130x504R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1DMA Read Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_ST_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62073Steering Tag (ST). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_RESERVED3_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62085Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62098Processing Hints (PH). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_1_DMA_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62112TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_1DMA_TRANSFER_SIZE_OFF_RDCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr621440x508R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1DMA Read Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62143DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_1DMA_SAR_LOW_OFF_RDCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr621650x50CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1DMA Read SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62164Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Read: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_1DMA_SAR_HIGH_OFF_RDCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr621830x510R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1DMA Read SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62182Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_1DMA_DAR_LOW_OFF_RDCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr622040x514R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1DMA Read DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62203Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Read: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_1DMA_DAR_HIGH_OFF_RDCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr622220x518R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1DMA Read DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62221Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_1DMA_LLP_LOW_OFF_RDCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr622440x51CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1DMA Read Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62243Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_1DMA_LLP_HIGH_OFF_RDCH_1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr622630x520R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1DMA Read Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62262Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_2DMA_CH_CONTROL1_OFF_WRCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr625700x600R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2DMA Write Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CB_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62283Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62302Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62319Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62340Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62361Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62382Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Write Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62394Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62412Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62425Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62437Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62453Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Write Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_WRCH_0).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED2_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62465Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62487Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62501Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62515Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62529Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62541Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62555Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62569Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_2DMA_CH_CONTROL2_OFF_WRCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr626260x604R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2DMA Write Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_ST_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62586Steering Tag (ST). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_RESERVED3_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62598Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62611Processing Hints (PH). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_2_DMA_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62625TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_2DMA_TRANSFER_SIZE_OFF_WRCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr626570x608R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2DMA Write Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62656DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_2DMA_SAR_LOW_OFF_WRCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr626780x60CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2DMA Write SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62677Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Write: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_2DMA_SAR_HIGH_OFF_WRCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr626960x610R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2DMA Write SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62695Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_2DMA_DAR_LOW_OFF_WRCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr627170x614R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2DMA Write DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62716Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Write: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_2DMA_DAR_HIGH_OFF_WRCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr627360x618R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2DMA Write DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62735Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_2DMA_LLP_LOW_OFF_WRCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr627580x61CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2DMA Write Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62757Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_2DMA_LLP_HIGH_OFF_WRCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr627770x620R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2DMA Write Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62776Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_2DMA_CH_CONTROL1_OFF_RDCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr630840x700R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2DMA Read Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CB_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62797Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62816Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62833Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62854Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62875Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62896Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Read Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62908Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62926Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62939Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62951Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62967Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Read Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_RDCH_0).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED2_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr62979Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63001Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63015Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63029Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63043Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63055Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63069Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63083Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_2DMA_CH_CONTROL2_OFF_RDCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr631400x704R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2DMA Read Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_ST_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63100Steering Tag (ST). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_RESERVED3_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63112Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63125Processing Hints (PH). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_2_DMA_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63139TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_2DMA_TRANSFER_SIZE_OFF_RDCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr631710x708R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2DMA Read Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63170DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_2DMA_SAR_LOW_OFF_RDCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr631920x70CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2DMA Read SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63191Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Read: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_2DMA_SAR_HIGH_OFF_RDCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr632100x710R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2DMA Read SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63209Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_2DMA_DAR_LOW_OFF_RDCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr632310x714R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2DMA Read DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63230Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Read: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_2DMA_DAR_HIGH_OFF_RDCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr632490x718R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2DMA Read DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63248Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_2DMA_LLP_LOW_OFF_RDCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr632710x71CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2DMA Read Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63270Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_2DMA_LLP_HIGH_OFF_RDCH_2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr632900x720R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2DMA Read Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63289Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_WRCH_3DMA_CH_CONTROL1_OFF_WRCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr635970x800R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3DMA Write Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CB_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63310Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63329Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63346Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63367Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63388Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63409Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Write Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63421Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63439Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63452Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63464Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63480Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Write Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_WRCH_0).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED2_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63492Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63514Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63528Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63542Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63556Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63568Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63582Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63596Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_WRCH_3DMA_CH_CONTROL2_OFF_WRCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr636530x804R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3DMA Write Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_ST_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63613Steering Tag (ST). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_RESERVED3_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63625Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63638Processing Hints (PH). This field is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_WRCH_3_DMA_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63652TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for wire DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_WRCH_3DMA_TRANSFER_SIZE_OFF_WRCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr636840x808R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3DMA Write Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63683DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_WRCH_3DMA_SAR_LOW_OFF_WRCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr637050x80CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3DMA Write SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63704Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Write: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_WRCH_3DMA_SAR_HIGH_OFF_WRCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr637230x810R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3DMA Write SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63722Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_WRCH_3DMA_DAR_LOW_OFF_WRCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr637440x814R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3DMA Write DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63743Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Write: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_WRCH_3DMA_DAR_HIGH_OFF_WRCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr637630x818R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3DMA Write DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63762Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_WRCH_3DMA_LLP_LOW_OFF_WRCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr637850x81CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3DMA Write Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63784Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_WRCH_3DMA_LLP_HIGH_OFF_WRCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr638040x820R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3DMA Write Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63803Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL1_OFF_RDCH_3DMA_CH_CONTROL1_OFF_RDCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr641110x900R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3DMA Read Channel Control 1 Register.falsefalsefalsefalseCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CB_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63824Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the CB of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 000x0R/WTCBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63843Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization".The DMA loads this field with the TCB of the linked list element.this field is not defined in a data LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 110x0R/WLLPPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63860Load Link Pointer (LLP). Used in linked list mode only.Indicates that this linked list element is a link element, and its LL element pointer dwords are pointing to the next (non-contiguous) element.The DMA loads this field with the LLP of the linked list element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 220x0R/WLIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63881Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 330x0R/WRIEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63902Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details, see "Interrupts and Error Handling".In LL mode, the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.This field is not defined in a link LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 440x0R/WCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63923Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel by writing to the Stop field of the "DMA Read Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).650x0R/WDMA_RESERVED0PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63935Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 770x0R/WCCSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63953Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 880x0R/WLLEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63966Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operationNote: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 990x0R/WDMA_RESERVED1PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63978Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 11100x0R/WDMA_FUNC_NUMPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr63994Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in the "DMA Read Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_RDCH_0).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 16120x00R/WDMA_RESERVED2PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED2_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr64006Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 21170x00R/WDMA_MEM_TYPEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr64028Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channelmemory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory typeFor more details, see "ACE-Lite Features and Limitations" section of theDatabook.Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 22220x0R/WDMA_NS_DSTPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr64042Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 23230x0R/WDMA_NS_SRCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr64056Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24240x0R/WDMA_ROPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr64070Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 25250x0R/WDMA_RESERVED5PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr64082Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 26260x0R/WDMA_TCPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr64096Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 29270x0R/WDMA_ATPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr64110Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31300x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_CH_CONTROL2_OFF_RDCH_3DMA_CH_CONTROL2_OFF_RDCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr641670x904R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3DMA Read Channel Control 2 Register.falsefalsefalsefalse--1600x0rDMA_STPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_ST_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr64127Steering Tag (ST). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 24170x00R/WDMA_RESERVED3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_RESERVED3_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr64139Reserved.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 28250x0R/WDMA_PHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_PH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr64152Processing Hints (PH). This field is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 30290x0R/WDMA_THPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_CH_CONTROL2_OFF_RDCH_3_DMA_TH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr64166TLP Processing Hints Present (TH). This filed is mapped onto the corresponding TLP field for application DMA MWr requests.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 31310x0R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_TRANSFER_SIZE_OFF_RDCH_3DMA_TRANSFER_SIZE_OFF_RDCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr641980x908R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3DMA Read Transfer Size Register.falsefalsefalsefalseDMA_TRANSFER_SIZEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr64197DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read channel transfer progresses. This field indicates the number bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.You can read this register to monitor the transfer progress, however in some scenarios this register is updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode).Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_LOW_OFF_RDCH_3DMA_SAR_LOW_OFF_RDCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr642190x90CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3DMA Read SAR Low Register.falsefalsefalsefalseSRC_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr64218Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of the remote memory. - DMA Read: The SAR is the address of the local memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_SAR_HIGH_OFF_RDCH_3DMA_SAR_HIGH_OFF_RDCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr642370x910R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3DMA Read SAR High Register.falsefalsefalsefalseSRC_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr64236Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_LOW_OFF_RDCH_3DMA_DAR_LOW_OFF_RDCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr642580x914R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3DMA Read DAR Low Register.falsefalsefalsefalseDST_ADDR_REG_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr64257Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the address of the local memory. - DMA Read: The DAR is the address of the remote memory.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_DAR_HIGH_OFF_RDCH_3DMA_DAR_HIGH_OFF_RDCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr642760x918R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3DMA Read DAR High Register.falsefalsefalsefalseDST_ADDR_REG_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr64275Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding dword of the LL element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_LOW_OFF_RDCH_3DMA_LLP_LOW_OFF_RDCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr642980x91CR/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3DMA Read Linked List Pointer Low Register.falsefalsefalsefalseLLP_LOWPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr64297Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is a data element; this field is incremented by 6 DWORDS. - When the current element is a link element; this field is overwritten by the LL Element Pointer of the element.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/WregisterPE0_DWC_pcie_ctl.DBI_Slave.PF0_DMA_CAP.DMA_LLP_HIGH_OFF_RDCH_3DMA_LLP_HIGH_OFF_RDCH_3PE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_OFFSETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_BYTE_OFFSETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr643170x920R/W0x00000000PE0_DWC_pcie_ctl_DBI_Slave_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3DMA Read Linked List Pointer High Register.falsefalsefalsefalseLLP_HIGHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_WIDTHPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_MSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_LSBPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_RANGEPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_RESETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_GETPE0_DWC_PCIE_CTL_DBI_SLAVE_PF0_DMA_CAP_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_SETDWC_pcie_unroll_wire_cpcie_usp_4x8.csr64316Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.Updated by the DMA to point to the next element in the transfer list as elements are consumed.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3100x00000000R/W
Addressmap Information for 'DWC_pcie_unroll_wire_cpcie_usp_4x8'